TY - JOUR
AU1 - Iwasaki, S
AU2 - Tanaka, M
AU3 - Yamanashi, Y
AU4 - Park, H
AU5 - Akaike, H
AU6 - Fujimaki, A
AU7 - Yoshikawa, N
AU8 - Takagi, N
AU9 - Murakami, K
AU1 - Honda, H
AU1 - Inoue, K
AB - We have designed a reconfigurable data-path (RDP) prototype based on thesingle-flux-quantum (SFQ) circuit. The RDP serves as an accelerator for a highperformance computer and is composed of many stages of the array of floating pointnumber processing units (FPUs) connected by reconfigurable operand routing networks(ORNs). The FPU array usually includes shift-registers (SRs) in order that the data isforwarded to the next stage without calculation. The data-path is reconfigured so as toreflect a long repeat instruction appearing in large-scale calculations. We can implementparallel and pipelined processing without memory access in such calculations, reducing therequired bandwidth between a memory and a microprocessor. The SFQ high speed networkswitches and bit-serial/slice FPUs realize reduction in the circuit areas and in the powerconsumption compared to semiconductor devices when we make up the RDP by using theSFQ circuit. As a first step of the development of the SFQ-RDP, we design a2 × 2 RDP prototype composed of double arrays of dual arithmetic logic units(ALUs). The prototype also has dual SRs in each array and four ORNs. Weuse bit-serial ALUs designed to operate at 25 GHz. Each ORN behaves like a4 × 2 crossbar switch. We have demonstrated the reconfiguration in the RDP prototype made upof 15050 Josephson junctions though only some of the functions of ALUs areavailable.
TI - Design of a reconfigurable data-path prototype in the single-flux-quantum circuit
JF - Superconductor Science and Technology
DO - 10.1088/0953-2048/20/11/S06
DA - 2007-11-01
UR - https://www.deepdyve.com/lp/iop-publishing/design-of-a-reconfigurable-data-path-prototype-in-the-single-flux-9YAByFNbob
SP - S328
VL - 20
IS - 11
DP - DeepDyve
ER -