TY - JOUR
AU - 
TI - Measuring Method for TSV-based Interconnect Resistance in 3D-SIC by Embedded Analog Boundary-Scan Circuit
JF - Transactions of The Japan Institute of Electronics Packaging
DO - 10.5104/jiepeng.7.140
DA - 2014-01-01
UR - https://www.deepdyve.com/lp/unpaywall/measuring-method-for-tsv-based-interconnect-resistance-in-3d-sic-by-8FkzR4jkkb
DP - DeepDyve
ER -