TY - JOUR
AU - Maity, N. P.
AB - This paper offers a unique novel adiabatic logic family for low-power applications named “Enhanced Positive Feedback Adiabatic Logic” (EPFAL). Traditional CMOS circuits and existing adiabatic logic techniques, such as Efficient Charge Recovery Logic (ECRL), Positive Feedback Adiabatic Logic (PFAL), 2N-2N2P, and other adiabatic design methodologies, face significant challenges related to high power dissipation and inefficient energy recovery during charging and discharging processes. EPFAL addresses these issues by substituting a four-phase trapezoidal power clock with a two-phase split-level sinusoidal power clock, which maximizes charge retrieval and reduces peak current movement, thereby minimizing power dissipation. The recommended circuit offers two complementary outputs since it is constructed on dual-rail encoded and sense-amplifier-structured quasi-adiabatic circuits that are powered by two-phase sinusoidal power-clock sources. The adiabatic and non-adiabatic losses that these circuits experience during the charging and recovery processes are what determine their efficacy. By maximizing charge retrieval and reducing peak current movement, the recommended EPFAL circuits reduce power dissipation. We analysed the behaviour of the EPFAL inverter circuit, modelling its corresponding charging RC equivalent circuit, and established a formula analytically for the total power loss of the circuit. Dynamic power consumptions are focused on and examined for fundamental gates: AND/NAND, OR/NOR, and XOR/XNOR, because adiabatically powered logic operation is preferred once the device's performance is more concerned with power optimization than with processing speed. Here even and odd parity generators as well as checker circuits are constructed and investigated based on the EPFAL. The analysis results demonstrate that the suggested EPFAL circuit outperforms existing reference circuits and has significantly reduced average power consumption. The simulations were performed using Cadence Virtuoso, utilizing the Low Power Berkeley Predictive Technology Model (45 nm LP_PTM) at various operating frequencies. When compared to traditional CMOS design techniques, the suggested EPFAL circuits save 82.14% and 77.53% of average power in odd parity generator and checker circuits, respectively.
TI - A novel adiabatic logic technique for low-power circuit applications
JF - Microsystem Technologies
DO - 10.1007/s00542-024-05842-5
DA - 2025-02-01
UR - https://www.deepdyve.com/lp/springer-journals/a-novel-adiabatic-logic-technique-for-low-power-circuit-applications-83g0RMmSR1
SP - 611
EP - 630
VL - 31
IS - 2
DP - DeepDyve
ER -