TY - JOUR
AU1 - Shi, Yunqi
AU2 - Xu, Siyuan
AU3 - Kai, Shixiong
AU4 - Lin, Xi
AU5 - Xue, Ke
AU6 - Yuan, Mingxuan
AU7 - Qian, Chao
AB - Abstract:Timing optimization during the global placement of integrated circuits has been a significant focus for decades, yet it remains a complex, unresolved issue. Recent analytical methods typically use pin-level timing information to adjust net weights, which is fast and simple but neglects the path-based nature of the timing graph. The existing path-based methods, however, cannot balance the accuracy and efficiency due to the exponential growth of number of critical paths. In this work, we propose a GPU-accelerated timing-driven global placement framework, integrating accurate path-level information into the efficient DREAMPlace infrastructure. It optimizes the fine-grained pin-to-pin attraction objective and is facilitated by efficient critical path extraction. We also design a quadratic distance loss function specifically to align with the RC timing model. Experimental results demonstrate that our method significantly outperforms the current leading timing-driven placers, achieving an average improvement of 40.5% in total negative slack (TNS) and 8.3% in worst negative slack (WNS), as well as an improvement in half-perimeter wirelength (HPWL).
TI - Timing-Driven Global Placement by Efficient Critical Path Extraction
JF - Computing Research Repository
DO - 10.48550/arxiv.2503.11674
DA - 2025-02-28
UR - https://www.deepdyve.com/lp/arxiv-cornell-university/timing-driven-global-placement-by-efficient-critical-path-extraction-83fIuNtxSI
VL - 2025
IS - 2503
DP - DeepDyve
ER -