TY - JOUR
AU - Mintzer, Les
AB - Abstract Distributed arithmetic techniques are the key to efficient implementation of DSP algorithms in FPGAs. The distributed arithmetic process is briefly described. A representative DSP design application in the form of an 8 tap FIR filter is offered for the Xilinx XC3042 field programmable logic array (FPGA). The design is presented in sufficient detail—from filter specifications via filter design software through detailed logic of salient data and control functions to obtain a realistic placing and routing of configurable logic block (CLBs) and in/out block (IOBs) components for simulation verification and performance evaluation vis-a-vis commercially available dedicated 8 tap FIR filter chips.
TI - FIR filters with field-programmable gate arrays
JF - Journal of Signal Processing Systems
DO - 10.1007/bf01607876
DA - 1993-08-01
UR - https://www.deepdyve.com/lp/springer-journals/fir-filters-with-field-programmable-gate-arrays-7kHjkK7o7O
SP - 119
EP - 127
VL - 6
IS - 2
DP - DeepDyve
ER -