TY - JOUR
AU - 
AB - International Journal of Computer Applications (0975 – 8887) Volume 178 – No. 21, June 2019 Cache Friendly and Capacity Conscious Scheduling in Multi-core Systems Sheela Kathavate N. K. Srinath Department of Computer Science and Engineering Department of Computer Science and Engineering Sir M. Visvesvaraya Institute of Technology R. V. College of Engineering Bangalore Bangalore different cores, cache miss could occur resulting in the ABSTRACT degradation of system performance. Hence, addressing shared Current generation high performance multi-core processors cache contention issue in CMPs becomes an issue to be have large shared cache memories. This shared cache memory addressed. is accessible by multiple cores. Concurrently running threads under each core do not always demand the entire capacity of the shared cache. Threads running on different cores accessing shared cache concurrently may result in higher cache miss rate and significant performance degradation due to inter-thread cache conflicts and lack of cache space. The cache capacity is the quantity of physical cache memory available with the processor. To achieve certain higher degree of processing performance on multi-core processors, efficient shared cache memory usage plays the defining role. The overall processor performance gets more sensitive to the problem of shortage of cache capacity, as 
TI - Cache Friendly and Capacity Conscious Scheduling in Multi-core Systems
JF - International Journal of Computer Applications
DO - 10.5120/ijca2019919077
DA - 2019-06-18
UR - https://www.deepdyve.com/lp/unpaywall/cache-friendly-and-capacity-conscious-scheduling-in-multi-core-systems-6mCU2q1MNW
DP - DeepDyve
ER -