TY - JOUR
AU - 
AB - Multiport memory cell using a dual-port memory cell provides required access to multi-processor- based applications. Simultaneous access can be provided using two-pass transistors, pair of bit lines, and a word line. Using specific word lines and bit lines of SRAM cell access can be provided by using dual ports memory. The single address of a memory cell can be accessed at a time during each clock pulse using single-port SRAM this drawback can be overcome by using dual-port RAM which supports concurrent read or write access at different addresses. Efficiency is improved by using dual-port RAM. Each processor can be made to operate at different clock frequencies thereby dual-port RAM will not have any limitations of access between the two ports. Keywords: Dual port memory, power consumption, write/read access, single port memory, Word line, bit line. 1. INTRODUCTION SRAM memories are the primary element of System-On-Chip (SOC). SRAM systems suffer from the disadvantage that they occupy more area which affects power and the yield. Frequently, the memories are implemented using SRAMs as they are robust, have high speed, and can be readily incorporated into logic circuits. Conceptually memory is an array of storage registers with distinct addresses, which is 
TI - Design and implementation of Dual-Port Memory
JO - Journal of University of Shanghai for Science and Technology
DO - 10.51201/jusst/21/06478
DA - 2021-06-26
UR - https://www.deepdyve.com/lp/unpaywall/design-and-implementation-of-dual-port-memory-5o3EW2jV05
DP - DeepDyve
ER -