TY - JOUR
AU - Páez-Monzón, Charles
AB - This work presents an academic RISC processor architecture, named DMN-6 that executes every instruction in the datapath. It concentrates all the movement, branch and alu instructions in the arithmetic-logic unit. The idea is to normalize the control signal generation for an integer functional unit. This is obtained by implementing a number of queue registers of different deepness around the datapath unit. These queues will control an assigned logic corresponding to a stage in the pipeline. The architecture reduces even more the complexity of a pipelined program execution. The main features are : Load/Store architecture, 4-stage pipeline, integer arithmetic, sixteen byte registers, internal separate data and instruction main memories, thirteen 16-bit instruction words.
TI - The RISC processor DMN-6: a unified data-control flow architecture
JF - ACM SIGARCH Computer Architecture News
DO - 10.1145/235688.235689
DA - 1996-09-01
UR - https://www.deepdyve.com/lp/association-for-computing-machinery/the-risc-processor-dmn-6-a-unified-data-control-flow-architecture-4LqcPGfjQh
SP - 3
VL - 24
IS - 4
DP - DeepDyve
ER -