TY - JOUR
AU - Rogdestvenski, Yu. V.
AB - The article considers the problem of developing synchronous and self-timed (ST) digital circuits tolerant to soft errors. Synchronous circuits traditionally use the “2-of-3” voting principle to ensure a single failure, resulting in three times the hardware costs. Due to dual-rail signal coding and two-phase control in ST circuits, duplication provides a soft error tolerance level 2.1 to 3.5 times higher than the triple modular redundant synchronous counterpart. The development of new high-precision software simulating microelectronic failure mechanisms will provide more accurate estimates for the electronic circuits’ failure tolerance.
TI - Failure-Tolerant Synchronous and Self-Timed Circuits Comparison
JO - Russian Microelectronics
DO - 10.1134/s1063739722080091
DA - 2022-12-01
UR - https://www.deepdyve.com/lp/springer-journals/failure-tolerant-synchronous-and-self-timed-circuits-comparison-47LUuc9JZ2
SP - 630
EP - 632
VL - 51
IS - 8
DP - DeepDyve
ER -