TY - JOUR
AU1 - Neitola, M.
AU2 - Rahkonen, T.
AB - A prototype analog correlator structure suitable for a WCDMA receiver was implemented. The advantages of this correlator are low power consumption compared to a digital correlator and small chip area. The target is to use such correlator as parallel correlators (fingers) of a RAKE receiver. The analog baseband correlator utilizes passive MOS-multipliers, a first-order low-pass continuous-time oversampling sigma–delta analog-to-digital converter and a second-order sinc type of decimation filter (for both I and Q input paths). The modulator sampling rate is twice the chip rate with oversampling ratios of 8–512 depending of the PN code length. The circuit was implemented in 0.8 μm CMOS-technology with a supply voltage of 2.8 V. The layout size is 345 μm×686 μm and the current drain is approximately 370 μA.
TI - An Analog Correlator for a WCDMA Receiver
JF - Analog Integrated Circuits and Signal Processing
DO - 10.1023/A:1008344813678
DA - 2004-10-19
UR - https://www.deepdyve.com/lp/springer-journals/an-analog-correlator-for-a-wcdma-receiver-3tdLaYiBJS
SP - 7
EP - 16
VL - 26
IS - 1
DP - DeepDyve
ER -