TY - JOUR
AU - Liu, Lianxi
AB - A clock generator circuit for a high-speed high-resolution pipelined A/D converter is presented. The circuit is realized by a delay locked loop (DLL), and a new differential structure is used to improve the precision of the charge pump. Meanwhile, a dynamic logic phase detector and a three transistor NAND logic circuit are proposed to reduce the output jitter by improving the steepness of the clock transition. The proposed circuit, designed by SMIC 0.18 m 3.3 V CMOS technology, is used as a clock generator for a 14 bit 100 MS/s pipelined ADC. The simulation results have shown that the duty cycle ranged from 10% to 90% and can be adjusted. The average duty cycle error is less than 1%. The lock-time is only 13 clock cycles. The active area is 0.05 mm2 and power consumption is less than 15 mW.
TI - A clock generator for a high-speed high-resolution pipelined A/D converter
JO - Journal of Semiconductors
DO - 10.1088/1674-4926/34/2/025003
DA - 2013-02-01
UR - https://www.deepdyve.com/lp/iop-publishing/a-clock-generator-for-a-high-speed-high-resolution-pipelined-a-d-1AqlttUJFr
SP - 025003
VL - 34
IS - 2
DP - DeepDyve
ER -