TY - JOUR
AU1 - Raisiardali, Alireza
AU2 - Iordanou, Konstantinos
AU3 - Kufel, Jedrzej
AU4 - Gudimetla, Kowshik
AU5 - Myny, Kris
AU6 - Ozer, Emre
AB - Abstract:This paper presents a methodology for automatically generating processors that support a subset of the RISC-V instruction set for a new class of applications at Extreme Edge. The electronics used in extreme edge applications must be power-efficient, but also provide additional qualities, such as low cost, conformability, comfort and sustainability. Flexible electronics, rather than silicon-based electronics, will be capable of meeting these qualities. For this purpose, we propose a methodology to generate RISPs (RISC-V instruction subset processors) customised to extreme edge applications and to implement them as flexible integrated circuits (FlexICs). The methodology is unique in the sense that verification is an integral part of design. The RISP methodology treats each instruction in the ISA as a discrete, fully functional, pre-verified hardware block. It automatically builds a custom processor by stitching together the hardware blocks of the instructions required by an application or a set of applications in a specific domain. This approach significantly reduces the processor verification and its time-to-market. We generate RISPs using this methodology for three extreme edge applications, and embedded applications from the Embench benchmark suite, synthesize them as FlexICs, and compare their power, performance and area to the baselines. Our results show that RISPs generated using this methodology achieve, on average, 30% reductions in power and area compared to a RISC-V processor supporting the full instruction set when synthesized, and are nearly 30 times more energy efficient with respect to Serv - the world's smallest 32-bit RISC-V processor. In addition, the full physical implementation of RISPs show up to 21% and 26% less area and power than Serv.
TI - Flexing RISC-V Instruction Subset Processors (RISPs) to Extreme Edge
JF - Computing Research Repository
DO - 10.48550/arxiv.2505.04567
DA - 2025-05-08
UR - https://www.deepdyve.com/lp/arxiv-cornell-university/flexing-risc-v-instruction-subset-processors-risps-to-extreme-edge-0ske0nsdwR
VL - 2025
IS - 2505
DP - DeepDyve
ER -