TY - JOUR
AU - Doss, M. Arun Noyal
AB - Introduction The need for energy also rises as a result of the rapid advancement of technology. The production of electricity relies heavily on fossil fuels almost everywhere in the world. However, the use of fossil fuels for power generation has declined due to a number of problems, such as air pollution and other environmental risks. Due to its greater availability, solar energy is the RES that is used the most frequently. Yet, partial shade situations may cause a decrease in the amount of electricity produced by PV. Traditional converters are often incorporated to overcome the drawbacks of low conversion efficiency and increased cost. A higher step-up DC-DC converter is used to convert the low voltage level to a higher voltage level for required applications [1, 2]. But due to a higher inrush current, the efficiency is reduced. The switching frequency of the system was raised to reduce the influence of inrush current and therefore the switches are subjected to high stress. The boost- type converters have a gain limitation because of their internal losses and also due to stress over the switches. It also has a negative effect on diodes, causing their efficiency to decline Hence, Converters with coupled inductance have been offered as a solution to this problem [3–6]. While switches are turned OFF, the leakage inductance develops a voltage spike. This in turn lowers the efficiency and causes high electromagnetic interference [EMI]. This can be overcome by active/passive clamped methods. Hence to override the above problems design of non-isolated boost converters were proposed [7–9]. However, it may leads to many disadvantages such as less reliability, more complexity and high cost. Moreover, the diode recovery issue is still a major issue in high gain applications [10–16]. Isolated Boost converters also exhibit higher voltage gain with a help of transformer. But the leakage inductance will leads to many problems like EMI etc., At the same time, the loss occurring in transformers will lead to high cost, low efficiency and more complexity in control strategy [17, 18]. The topology of the Boost converter with fly- back combination is designed to attain high voltage gain. This design is feasibly simple when compared to other existing converters. But, maintaining voltage balance among the capacitor is tedious [19]. The efficiency of the converter is significantly influenced by the diode’s reverse recovery loss. The reverse recovery loss can be decreased when the boost converter operates in critical current mode or on a discontinuous current model [20]. This will increase current ripples and stress in the input current. In order to defeat this, a bulky filter has to be implemented. Hence, it is not suitable for high-power applications [21]. Interleaved Boost Converters (IBC) can be employed for enhancement in both power level and density, with low thermal stress delivery. Thus, it exhibits less ripple current for a duty cycle ratio below 0.5 [22–24]. Conversely, it exhibits certain drawbacks, when implemented in PV-grid connected system. Simultaneously, voltage stress over the switches is high and hence, there will be a low efficiency. To achieve higher gain a Non-Isolated with diode capacitor is designed [25]. To attain this, VM units extended to ‘n’ stages. The level can be increased by increasing the duty cycle and VM units. Thus, it exhibits an efficiency about 93.6%. A new converter using triple mode is invented [26], but it requires increased components to attain higher voltage gain. In practical utilization, its efficiency is about 93.86% at 500 W. A novel converter called interleaved MBC with VM cells is developed. When load power is about 300W, its efficiency is 93.56%. The presence of diodes in this circuit results in a high loss. In quasi-Z-source converters, an input current remains continuous and hence stress over the switches and capacitors is very low. But they do not exhibit high gain [27, 28]. A converter with higher gain and lower stress on switches was designed. Its efficiency is about 93.6% (@ 66 W). This converter exhibits high gain at a lower duty ratio. Its highest gain is above 12 times ideal conditions with a duty ratio 0.6. But in practice, it depends upon parasitic values of components and load [29]. Similar to step-down and step-up mode efficiency is 91.2% and 89%, respectively. The greatest efficiency, at an output current of 0.6 A while in boost mode, is 93.9 [30]. A new converter that exhibits continuous input current is suggested in [31]. However, at larger duty ratios, the voltage gain is restricted. A single-stage AC/DC FLC with synchronous rectification(SR) function and three output windings is used in order to enhance the cross-regulation and efficiency [32]. Its maximum efficiency is 87%, around 3% greater than a traditional Schottky diode. This converter exhibits high gains in theory. Whenever blocking voltage occurs, it exhibits a significant reverse voltage over the switches. It is due to energy stored in its leaking inductance. As a result, dampening circuits are necessary, which increases costs and also reduces efficiency. Furthermore, a high gain ratio may cause the output diode to reach its higher peak voltage during commutations. In order to overcome the defect of the converter topology, hybrid combinations of converters are introduced [33]. A coupled inductor (CI) and a voltage multiplier (VM) are used without a high-duty cycle to increase ultra-high voltage gain. A regenerative passive clamp capacitor linked in parallel to the switch and the leaking inductor of the CI recycles the magnetic energy stored there, assisting in limiting the maximum voltage across the switch. Thus, it is recommended to uses a switch with low static drain to source ON-resistance to reduce conduction losses in switches and improves efficiency [34]. A flyback-forward DC–DC converter with zero current switching’s is suggested in this work. The efficiency is increased by using an auxiliary circuit without any additional switches to offer gentle switching conditions [35]. DC-DC “Switching” power converters are a common class of linear, time-variant devices that are challenging to model and simulate. They are created to change a source of direct current (DC) from one voltage level to another while keeping it stable within predetermined parameters. Because of parasitic characteristics a significant impact on how these circuits really operate in accurate time and frequency domain, simulation results depend on how well the converter circuit non-idealities are modelled [36]. Thus, in this work, a novel hybrid converter combining boost and FBC is implemented. The proposed converter features two outputs in series: a flyback type that symbolizes high gain and a boost type that makes use of the energy in the leakage inductance. The wide variety of conversion ratios and steady input current of the proposed IBFC converter are ideal for applications involving renewable energy. The proposed converter advantages are Elevated voltage gain Switching stress is low Higher Efficiency Regulated output voltage The above advantages are suitably confirmed by mathematical modelling, simulation using MATLAB/SIMULINK and Experimental prototype. This article is structured as follows. The proposed system’s modelling is discussed in Section 2. A feasibility analysis of this converter is done in Section 3. Finally, Section 4 discusses a brief conclusion. Modeling of the proposed converter Converter The proposed converter topology is shown in Fig 1, which is a hybrid of an FLC and a boost converter. A VM cell topology is incorporated in the converter to boost the voltage. It also reduces the di/dt stress on diodes. Download: PPT PowerPoint slide PNG larger image TIFF original image Fig 1. Representation of the proposed converter. https://doi.org/10.1371/journal.pone.0287770.g001 Fig 2 depicts the proposed converter Equivalent circuit. Download: PPT PowerPoint slide PNG larger image TIFF original image Fig 2. Proposed converter equivalent circuit. https://doi.org/10.1371/journal.pone.0287770.g002 Steady state examination The assumptions are considered here in order to simplify the analysis of the proposed circuit. The capacitors C1 and C2 are considered as same value. (VC1 = VC2 = VC); The magnetising inductance (Lm) is taken into account as large and hence, the current across it remains constant. Correspondingly, the voltage drop across the leakage inductor (L2), was neglected. The volt-sec balance principle is used to derive a converter’s voltage gain. The operating modes of this converter is depicted in Figs 3–6. Download: PPT PowerPoint slide PNG larger image TIFF original image Fig 3. Mode 2. https://doi.org/10.1371/journal.pone.0287770.g003 Download: PPT PowerPoint slide PNG larger image TIFF original image Fig 4. Mode 3. https://doi.org/10.1371/journal.pone.0287770.g004 Download: PPT PowerPoint slide PNG larger image TIFF original image Fig 5. Mode 4. https://doi.org/10.1371/journal.pone.0287770.g005 Download: PPT PowerPoint slide PNG larger image TIFF original image Fig 6. Mode 5. https://doi.org/10.1371/journal.pone.0287770.g006 Mode 1 (t0 − t1) At this time (t = t0), all charges in the capacitors are negated and remains as ideal as Fig 1. Mode 2 (t1 − t2) During t = t1, switch S is turned on at zero voltage. As a result, the current across ilm is given as (1) Where, n—Coupled Inductor turn’s ratio. During S ON, current at the secondary side of CI starts charging SC (C1 and C2) in this circuit. Thus, il2, charges C3 and C4. (2) Because il2 is negative at that point, its magnitude begins to diminish. At this condition, the operation of the circuit is shown in Fig 3. Mode 3 (t2 − t3) In this Fig 4, il2 approaches zero at this point. ie. D1 and D2 remains turn off. This reduces the reverse recovery problems. As a result of shift in il2, C1 and C2 discharges to C3. As a result, the current through the inductor im is shown as (3) Mode 4 (t3 − t4) S is turned off during t = t3. VC4 is charged by the current flowing across im and is depicted in Fig 5. Due to the fact that VO is greater than VC4, the voltage stress on S is relatively modest. As a result, no additional clamp circuit is required. During this interval, the current (im) is derived as (4) Mode 5 (t4 − t5) In this Fig 6, il2 is reversed and im is (5) Mode 6 (t5 − t6) The current im remains same as it was in the preceding mode at t = t5. Fig 7 depicts the different modes of operation of the converter. Download: PPT PowerPoint slide PNG larger image TIFF original image Fig 7. Modes of operation. https://doi.org/10.1371/journal.pone.0287770.g007 Analysis and design considerations Voltage gain. The converter’s output voltage Vo can be computed as (6) The association of V1, VO, VC3, VC and VC4 may then be obtained using voltage second balancing analysis over (Lm and L2) in modes 3 and 6. (7) (8) Then by rearranging Eqs (3), (6), (7) and (8) the gain of this converter can be derived as, (9) According to the preceding equation, By varying turns ratio of mutual inductance, the gain can be altered. Voltage stress analysis Due to the fact that VO is greater than VC4, voltage stress over S is relatively small. Similarly, all diode’s voltage stress (D1, D2) is determined by VC3 and VC. A current stress across diode D3 can be expressed as, (10) Similarly, the current stress across D1 and D2 is given by as, (11) To examine the coupling factor influence, a specific analysis was performed on a magnetic coupled inductor based boost converter. High voltages can be obtained by utilizing a coupled inductors. In reality, as the insulation voltage and fabrication limitations increase, the coupling factor drops. Design of inductors The inductor’s turn ratio is critical for the converter’s voltage gain. As a result, the turns ratio should be chosen in such a way that it influences the inductor’s loss and size. The magnetic core’s non-saturation restriction could be utilised to calculate the minimum number of turns on primary side (12) where, Bs-Flux density n0–No. of turns on primary side Ae-Cross section (Magnetic Core). EiTn-Maximum volt-second (Primary Side). A lower turns ratio indicates a) low copper and winding loss b) A smaller coupled inductor. As a result, a low ratio of turns is preferred. Similarly, the inductors namely Lm and Lk1 should be selected in such a way to reduce the di/dt stress over the diodes. In designing, the selection of proper rating for all the components in the converter is essential. More importance is therefore given for designing the converter components. While designing an inductor, the inductor ripple current(IL) must be considered. Thus, it can be determined using a formula (13) (14) (15) Where L1 = L2 Design of capacitors (16) Assumed C3 = C4. Voltage Multiplier cells: C1&C2 (17) (18) Efficient and transient analysis The following equations are used to calculate the theoretical loss of the proposed topologies. Conduction losses of passive elements, conduction and switching losses of diodes and power semiconductor are taken into consideration. (19) Conducting losses of switches (20) Conducting losses of diodes can be derived from the following equation (21) Switching losses of switches (22) Switching losses of diodes can be derived from the following equation (23) Therefore, both the switching and conduction losses in the switch and diode are expressed as, (24) Diode loss considering diode voltage and resistance is given below and reverse recovery loss (PDsw) is small contributor and therefore neglected, (25) (26) Similarly, the power loss and capacitor loss are given as (27) (28) (29) (30) Total Loss Fig 8 depicts the percentage of losses occurred due to various components in this. The converter’s efficiency is about 90.95%. As this converter has more number of diodes, diode loss is significantly high in this proposed architecture. Download: PPT PowerPoint slide PNG larger image TIFF original image Fig 8. Losses of the proposed topology. https://doi.org/10.1371/journal.pone.0287770.g008 Voltage ripple The ripple voltage on VC can be derived as, (31) where, Cc—switch capacitance, C1 and C2. According to the Eq (31), a large capacitance is required to overcome the voltage ripple problem. As a result, Cc can be calculated based on the desired voltage ripple. It also applicable for output capacitors. State space averaging and modeling The supportive parameters, as shown in Fig 1, independent state variables and the state space vector is expressed as follows: (32) This equation represents the system output in terms of current state and input, forms a state space equation of the system which can be represented as Thus, it can be also represented as Controller implementation FOPID controller. Fractional PID controllers have been utilized to enhance the system control in industrial applications. It is a feedback controller that can be utilized in a various applications. As it has three parameters in its structure, it is referred as three modes controller. The goal of the developed controller is to reduce integral square error and hence boost dynamic response. The values of the three action’s parameters can be depicted in terms of time: P—Current error, I—Addition of prior errors D—Forecast of future errors. A Fractional calculus based classic PID Controller is shown in Fig 9. Download: PPT PowerPoint slide PNG larger image TIFF original image Fig 9. Closed loop FOPID controller using MATLAB/Simulink model. https://doi.org/10.1371/journal.pone.0287770.g009 The gain constant Ki and λ can be obtained from the equations, and then, Kp can be obtained. After finding α, the parameters of the simplified FOPID controller can be obtained using the above discussed specifications. Fig 9 depicts Closed loop model of FOPID Controller using MATLAB/Simulink model. The transfer function of PIλDμ can be depicted as, (33) Where λ & μ—Real numbers (Positive) Kp, Ki & Kd—Gain constants. While substituting λ and μ = 1, the Eq (33) becomes PID controller and the controller acts like a PID controller. Similarly, by substituting λ = 1, μ = 0, PI can be obtained. When λ = 0, μ = 1, it behaves like a PD controller. Converter The proposed converter topology is shown in Fig 1, which is a hybrid of an FLC and a boost converter. A VM cell topology is incorporated in the converter to boost the voltage. It also reduces the di/dt stress on diodes. Download: PPT PowerPoint slide PNG larger image TIFF original image Fig 1. Representation of the proposed converter. https://doi.org/10.1371/journal.pone.0287770.g001 Fig 2 depicts the proposed converter Equivalent circuit. Download: PPT PowerPoint slide PNG larger image TIFF original image Fig 2. Proposed converter equivalent circuit. https://doi.org/10.1371/journal.pone.0287770.g002 Steady state examination The assumptions are considered here in order to simplify the analysis of the proposed circuit. The capacitors C1 and C2 are considered as same value. (VC1 = VC2 = VC); The magnetising inductance (Lm) is taken into account as large and hence, the current across it remains constant. Correspondingly, the voltage drop across the leakage inductor (L2), was neglected. The volt-sec balance principle is used to derive a converter’s voltage gain. The operating modes of this converter is depicted in Figs 3–6. Download: PPT PowerPoint slide PNG larger image TIFF original image Fig 3. Mode 2. https://doi.org/10.1371/journal.pone.0287770.g003 Download: PPT PowerPoint slide PNG larger image TIFF original image Fig 4. Mode 3. https://doi.org/10.1371/journal.pone.0287770.g004 Download: PPT PowerPoint slide PNG larger image TIFF original image Fig 5. Mode 4. https://doi.org/10.1371/journal.pone.0287770.g005 Download: PPT PowerPoint slide PNG larger image TIFF original image Fig 6. Mode 5. https://doi.org/10.1371/journal.pone.0287770.g006 Mode 1 (t0 − t1) At this time (t = t0), all charges in the capacitors are negated and remains as ideal as Fig 1. Mode 2 (t1 − t2) During t = t1, switch S is turned on at zero voltage. As a result, the current across ilm is given as (1) Where, n—Coupled Inductor turn’s ratio. During S ON, current at the secondary side of CI starts charging SC (C1 and C2) in this circuit. Thus, il2, charges C3 and C4. (2) Because il2 is negative at that point, its magnitude begins to diminish. At this condition, the operation of the circuit is shown in Fig 3. Mode 3 (t2 − t3) In this Fig 4, il2 approaches zero at this point. ie. D1 and D2 remains turn off. This reduces the reverse recovery problems. As a result of shift in il2, C1 and C2 discharges to C3. As a result, the current through the inductor im is shown as (3) Mode 4 (t3 − t4) S is turned off during t = t3. VC4 is charged by the current flowing across im and is depicted in Fig 5. Due to the fact that VO is greater than VC4, the voltage stress on S is relatively modest. As a result, no additional clamp circuit is required. During this interval, the current (im) is derived as (4) Mode 5 (t4 − t5) In this Fig 6, il2 is reversed and im is (5) Mode 6 (t5 − t6) The current im remains same as it was in the preceding mode at t = t5. Fig 7 depicts the different modes of operation of the converter. Download: PPT PowerPoint slide PNG larger image TIFF original image Fig 7. Modes of operation. https://doi.org/10.1371/journal.pone.0287770.g007 Analysis and design considerations Voltage gain. The converter’s output voltage Vo can be computed as (6) The association of V1, VO, VC3, VC and VC4 may then be obtained using voltage second balancing analysis over (Lm and L2) in modes 3 and 6. (7) (8) Then by rearranging Eqs (3), (6), (7) and (8) the gain of this converter can be derived as, (9) According to the preceding equation, By varying turns ratio of mutual inductance, the gain can be altered. Voltage gain. The converter’s output voltage Vo can be computed as (6) The association of V1, VO, VC3, VC and VC4 may then be obtained using voltage second balancing analysis over (Lm and L2) in modes 3 and 6. (7) (8) Then by rearranging Eqs (3), (6), (7) and (8) the gain of this converter can be derived as, (9) According to the preceding equation, By varying turns ratio of mutual inductance, the gain can be altered. Voltage stress analysis Due to the fact that VO is greater than VC4, voltage stress over S is relatively small. Similarly, all diode’s voltage stress (D1, D2) is determined by VC3 and VC. A current stress across diode D3 can be expressed as, (10) Similarly, the current stress across D1 and D2 is given by as, (11) To examine the coupling factor influence, a specific analysis was performed on a magnetic coupled inductor based boost converter. High voltages can be obtained by utilizing a coupled inductors. In reality, as the insulation voltage and fabrication limitations increase, the coupling factor drops. Design of inductors The inductor’s turn ratio is critical for the converter’s voltage gain. As a result, the turns ratio should be chosen in such a way that it influences the inductor’s loss and size. The magnetic core’s non-saturation restriction could be utilised to calculate the minimum number of turns on primary side (12) where, Bs-Flux density n0–No. of turns on primary side Ae-Cross section (Magnetic Core). EiTn-Maximum volt-second (Primary Side). A lower turns ratio indicates a) low copper and winding loss b) A smaller coupled inductor. As a result, a low ratio of turns is preferred. Similarly, the inductors namely Lm and Lk1 should be selected in such a way to reduce the di/dt stress over the diodes. In designing, the selection of proper rating for all the components in the converter is essential. More importance is therefore given for designing the converter components. While designing an inductor, the inductor ripple current(IL) must be considered. Thus, it can be determined using a formula (13) (14) (15) Where L1 = L2 Design of capacitors (16) Assumed C3 = C4. Voltage Multiplier cells: C1&C2 (17) (18) Efficient and transient analysis The following equations are used to calculate the theoretical loss of the proposed topologies. Conduction losses of passive elements, conduction and switching losses of diodes and power semiconductor are taken into consideration. (19) Conducting losses of switches (20) Conducting losses of diodes can be derived from the following equation (21) Switching losses of switches (22) Switching losses of diodes can be derived from the following equation (23) Therefore, both the switching and conduction losses in the switch and diode are expressed as, (24) Diode loss considering diode voltage and resistance is given below and reverse recovery loss (PDsw) is small contributor and therefore neglected, (25) (26) Similarly, the power loss and capacitor loss are given as (27) (28) (29) (30) Total Loss Fig 8 depicts the percentage of losses occurred due to various components in this. The converter’s efficiency is about 90.95%. As this converter has more number of diodes, diode loss is significantly high in this proposed architecture. Download: PPT PowerPoint slide PNG larger image TIFF original image Fig 8. Losses of the proposed topology. https://doi.org/10.1371/journal.pone.0287770.g008 Voltage ripple The ripple voltage on VC can be derived as, (31) where, Cc—switch capacitance, C1 and C2. According to the Eq (31), a large capacitance is required to overcome the voltage ripple problem. As a result, Cc can be calculated based on the desired voltage ripple. It also applicable for output capacitors. State space averaging and modeling The supportive parameters, as shown in Fig 1, independent state variables and the state space vector is expressed as follows: (32) This equation represents the system output in terms of current state and input, forms a state space equation of the system which can be represented as Thus, it can be also represented as Controller implementation FOPID controller. Fractional PID controllers have been utilized to enhance the system control in industrial applications. It is a feedback controller that can be utilized in a various applications. As it has three parameters in its structure, it is referred as three modes controller. The goal of the developed controller is to reduce integral square error and hence boost dynamic response. The values of the three action’s parameters can be depicted in terms of time: P—Current error, I—Addition of prior errors D—Forecast of future errors. A Fractional calculus based classic PID Controller is shown in Fig 9. Download: PPT PowerPoint slide PNG larger image TIFF original image Fig 9. Closed loop FOPID controller using MATLAB/Simulink model. https://doi.org/10.1371/journal.pone.0287770.g009 The gain constant Ki and λ can be obtained from the equations, and then, Kp can be obtained. After finding α, the parameters of the simplified FOPID controller can be obtained using the above discussed specifications. Fig 9 depicts Closed loop model of FOPID Controller using MATLAB/Simulink model. The transfer function of PIλDμ can be depicted as, (33) Where λ & μ—Real numbers (Positive) Kp, Ki & Kd—Gain constants. While substituting λ and μ = 1, the Eq (33) becomes PID controller and the controller acts like a PID controller. Similarly, by substituting λ = 1, μ = 0, PI can be obtained. When λ = 0, μ = 1, it behaves like a PD controller. FOPID controller. Fractional PID controllers have been utilized to enhance the system control in industrial applications. It is a feedback controller that can be utilized in a various applications. As it has three parameters in its structure, it is referred as three modes controller. The goal of the developed controller is to reduce integral square error and hence boost dynamic response. The values of the three action’s parameters can be depicted in terms of time: P—Current error, I—Addition of prior errors D—Forecast of future errors. A Fractional calculus based classic PID Controller is shown in Fig 9. Download: PPT PowerPoint slide PNG larger image TIFF original image Fig 9. Closed loop FOPID controller using MATLAB/Simulink model. https://doi.org/10.1371/journal.pone.0287770.g009 The gain constant Ki and λ can be obtained from the equations, and then, Kp can be obtained. After finding α, the parameters of the simplified FOPID controller can be obtained using the above discussed specifications. Fig 9 depicts Closed loop model of FOPID Controller using MATLAB/Simulink model. The transfer function of PIλDμ can be depicted as, (33) Where λ & μ—Real numbers (Positive) Kp, Ki & Kd—Gain constants. While substituting λ and μ = 1, the Eq (33) becomes PID controller and the controller acts like a PID controller. Similarly, by substituting λ = 1, μ = 0, PI can be obtained. When λ = 0, μ = 1, it behaves like a PD controller. Results and discussion The open loop and closed loop performance of the proposed converter is verified using MATLAB/SIMULINK Model. Table 1 lists the components utilized in the converter. Download: PPT PowerPoint slide PNG larger image TIFF original image Table 1. Design parameters of converter. https://doi.org/10.1371/journal.pone.0287770.t001 The open loop converter output voltage and current is portrayed in Fig 10. Download: PPT PowerPoint slide PNG larger image TIFF original image Fig 10. Output voltage /current (open loop). https://doi.org/10.1371/journal.pone.0287770.g010 Voltage stress over the switch is presented in Fig 11. Download: PPT PowerPoint slide PNG larger image TIFF original image Fig 11. Voltage across the switch. https://doi.org/10.1371/journal.pone.0287770.g011 The voltage across the MOSFET switch is an average of 150 V, which is lower than that of the output voltage. The average voltage on VM cell diodes such as D1, D2 is 20V. Hence, it is concluded that as voltage stress over the switch remains low ensures high efficiency. The voltage across the capacitor C3 and C4 is depicted in Fig 12. Download: PPT PowerPoint slide PNG larger image TIFF original image Fig 12. Voltage across C3 and C4. https://doi.org/10.1371/journal.pone.0287770.g012 The current across the inductor L1 and L2 is depicted in Fig 13. Download: PPT PowerPoint slide PNG larger image TIFF original image Fig 13. Current across inductor. https://doi.org/10.1371/journal.pone.0287770.g013 Fig 13 depicts the current across the primary and secondary side of a CI. From the figure, it is observed that whenever primary coil of coupled inductor is energized, secondary coil receives energy due to mutual inductance between coupled inductor. Thus, an analysis of this converter under closed loop mode is portrayed in Fig 14. In this closed loop study, to ensure the system’s stability, a FOPID controller is implemented. Regardless of variations in input voltage/load, it maintains a constant voltage at the output.. The gains of the converter are determined using ZN method. Download: PPT PowerPoint slide PNG larger image TIFF original image Fig 14. Output voltage /current of the converter (FOPID controller). https://doi.org/10.1371/journal.pone.0287770.g014 Parameter settings considered for FOPID controller are as follows Kp = 0.5010, Ki = 4.8940, Kd = 4.8940, λ = 1 and μ = 0.99. There is less output variability when compared to open loop control. The results reveal that the FOPID controller is more efficient than a typical controller.Both open loop and closed loop test of the proposed converter show higher voltage gain. Thus, to analyse the effect of stability of the converter, bode plot analysis have been carried out. Fig 15 depicts the bode plot diagram of the proposed converter. Download: PPT PowerPoint slide PNG larger image TIFF original image Fig 15. Bode plot. https://doi.org/10.1371/journal.pone.0287770.g015 The value of gain and phase margin is observed from the bode plot (Gm = 1.1657e−11, Pm = 2.0149 for open loop; Gm = 3.0215e-16, Pm = 9.6520 for closed loop) and are positive. Hence the proposed converter remains stable and controllable in closed loop also. Performance analysis of the converter with PV module Fig 16 depicts the PV integrated proposed converter. Download: PPT PowerPoint slide PNG larger image TIFF original image Fig 16. Proposed converter with PV panel. https://doi.org/10.1371/journal.pone.0287770.g016 Thus, the PV modelling for the proposed configuration is depicted below The solar cell is the basic component of PV arrays. the P-N junction that transforms light energy into electrical current. When it comes into contact with light, the photons are absorbed. Only photons with energies bigger than the energy gaps are absorbed, hence the absorbed photons create electron-hole pairs. The electric fields are influenced by this method of photons with electron hole pairs, which also produces current that is proportionate to solar radiation. The PV cell Equivalent circuit model is stated in Fig 17. Download: PPT PowerPoint slide PNG larger image TIFF original image Fig 17. Equivalent circuit of a PV cell. https://doi.org/10.1371/journal.pone.0287770.g017 The PV module is formed by connecting numerous PV cells. PV modules are connected in series and parallel to create the PV array. The following equation represents a PV array as a mathematical model. (34) where Iph—Photo current I—output current PV array V—output voltage PV array ns—series number of cells np—parallel number of cells q—charge K—Boltzmann’s constant [8.62 × 10−5 eV/K] A—p-n junction Ideality Factor. It ranges between 1–5. T—cell temperature (K) Irs—reverse saturation current. Thus the PV power can be calculated using: (35) The irradiance, environmental conditions and the currents drawn out of the cells optimizes the power emitted by the PV systems. Few applications demands power more than the offered limit of the PV systems. The appliances like usage of power grid battery charging or electric motor usage etc. demands more power from the PV system. In these cases the power from the PV system has to be maximized which could be done using the power conversion system. Fig 18 depicts the performance of the converter under different irradiance condition. Download: PPT PowerPoint slide PNG larger image TIFF original image Fig 18. Converter voltage and PV power with respect to varying irradiance. https://doi.org/10.1371/journal.pone.0287770.g018 Fig 19 shows the voltage of the proposed converter. Download: PPT PowerPoint slide PNG larger image TIFF original image Fig 19. Voltage obtained from the converter. https://doi.org/10.1371/journal.pone.0287770.g019 Performance analysis of the converter with PV module Fig 16 depicts the PV integrated proposed converter. Download: PPT PowerPoint slide PNG larger image TIFF original image Fig 16. Proposed converter with PV panel. https://doi.org/10.1371/journal.pone.0287770.g016 Thus, the PV modelling for the proposed configuration is depicted below The solar cell is the basic component of PV arrays. the P-N junction that transforms light energy into electrical current. When it comes into contact with light, the photons are absorbed. Only photons with energies bigger than the energy gaps are absorbed, hence the absorbed photons create electron-hole pairs. The electric fields are influenced by this method of photons with electron hole pairs, which also produces current that is proportionate to solar radiation. The PV cell Equivalent circuit model is stated in Fig 17. Download: PPT PowerPoint slide PNG larger image TIFF original image Fig 17. Equivalent circuit of a PV cell. https://doi.org/10.1371/journal.pone.0287770.g017 The PV module is formed by connecting numerous PV cells. PV modules are connected in series and parallel to create the PV array. The following equation represents a PV array as a mathematical model. (34) where Iph—Photo current I—output current PV array V—output voltage PV array ns—series number of cells np—parallel number of cells q—charge K—Boltzmann’s constant [8.62 × 10−5 eV/K] A—p-n junction Ideality Factor. It ranges between 1–5. T—cell temperature (K) Irs—reverse saturation current. Thus the PV power can be calculated using: (35) The irradiance, environmental conditions and the currents drawn out of the cells optimizes the power emitted by the PV systems. Few applications demands power more than the offered limit of the PV systems. The appliances like usage of power grid battery charging or electric motor usage etc. demands more power from the PV system. In these cases the power from the PV system has to be maximized which could be done using the power conversion system. Fig 18 depicts the performance of the converter under different irradiance condition. Download: PPT PowerPoint slide PNG larger image TIFF original image Fig 18. Converter voltage and PV power with respect to varying irradiance. https://doi.org/10.1371/journal.pone.0287770.g018 Fig 19 shows the voltage of the proposed converter. Download: PPT PowerPoint slide PNG larger image TIFF original image Fig 19. Voltage obtained from the converter. https://doi.org/10.1371/journal.pone.0287770.g019 Comparative analysis The formulated topology is compared with several other recent converter structures in this section. In order to demonstrate the converter’s benefits, it is compared to other high step-up converters that have been shown. Table 2 demonstrates that the proposed configuration enables semiconductors with a minimum number of components constant input current and soft switching circumstances. Download: PPT PowerPoint slide PNG larger image TIFF original image Table 2. Performance comparison. https://doi.org/10.1371/journal.pone.0287770.t002 The gain of the converter is increased by using a CI in it. i.e., as shown in the table above, more than ten times as much as a normal converter. This can be utilised in Applications of PV Systems. The voltage across the switch in this converter is fairly modest when compared to a boost converter. The proposed converter has decreased conduction loss. In Fig 20 to prove the efficiency of the proposed converter, a comparative analysis has been made with the existing converter topologies. Fig 21 shows the comparison of voltage gain and stress across the switch of the CI based converter. Download: PPT PowerPoint slide PNG larger image TIFF original image Fig 20. Efficiency comparison. https://doi.org/10.1371/journal.pone.0287770.g020 Download: PPT PowerPoint slide PNG larger image TIFF original image Fig 21. Comparison of voltage gain vs duty cycle and voltages stress across switch vs duty cycle. https://doi.org/10.1371/journal.pone.0287770.g021 In comparison to the typical converter, the Proposed converter’s switch is subjected to much less voltage stress, which also aids in the choice of a MOSFET switch with a low rds-on. This lowers switching and conduction losses and hence achieved high conversion efficiency [34, 38]. Table 3 compares the proposed converter with various conventional converters based on the analysis of voltage gain and Duty cycle. Download: PPT PowerPoint slide PNG larger image TIFF original image Table 3. Duty cycle vs voltage gain. https://doi.org/10.1371/journal.pone.0287770.t003 Experimental results Fig 22 shows a Electrical diagram model of the proposed converter. Fig 23 depicts the implemented converter in the laboratory setup using FOPID controller. The proposed IBFC Converter is tested for its 18V input voltage and 220V output voltage with 100W in order to validate the theoretical analysis in the CCM mode of operation. The prototype is scaled down and put to the test to show the converter’s superior performance. Fig 24A–24D shows a snapshot of the experimental setup together with the findings and a performance analysis of the converter and controller. The pulse generator operates with a duty cycle of 0.63 and an input voltage of 18V to produce an output voltage of 220V. It has two stages: the boost converter is the first stage, and the flyback converter is the second. A single switch MOSFET powers two stages. The effectiveness of the proposed converter is calculated using the formula (output power/input power) * 100 = 89.75%. Download: PPT PowerPoint slide PNG larger image TIFF original image Fig 22. Electrical diagram model of proposed converter. https://doi.org/10.1371/journal.pone.0287770.g022 Download: PPT PowerPoint slide PNG larger image TIFF original image Fig 23. Prototype model of converter. https://doi.org/10.1371/journal.pone.0287770.g023 Download: PPT PowerPoint slide PNG larger image TIFF original image Fig 24. Converter output with controller (A) Input voltage waveform (B) Voltage across the switch (with Controller) (C) Output Voltage (D) Voltage across D1 and D2. https://doi.org/10.1371/journal.pone.0287770.g024 Performance analysis of the converter with controller The output of the converter with controller is depicted in Fig 24A–24D. From the figure, it is witnessed that when switch turns ON, resonance occurs with voltage spike. As a result, conduction loss becomes low. Performance analysis of the converter with controller The output of the converter with controller is depicted in Fig 24A–24D. From the figure, it is witnessed that when switch turns ON, resonance occurs with voltage spike. As a result, conduction loss becomes low. Conclusion This paper implements an integrated flyback and boost converter. In comparison to standard integrated DC-DC converter topologies, the proposed converter is modular and takes into fewer number of power devices. This works advances a single stage dc-dc converter by merging flyback and boost converters by utilising a single switch and also hybrid converter based optimal controller is proposed. The distinct proposed converters features are as follows The proposed converter is modelled with high elevated gain and less switching stress due to single switch. It comprises the integration of the flyback, boost, and switched network in the flyback converter’s secondary side. The converter’s gain is doubled by the SC. There is reduced switching and conduction loss compared to that of the conventional converter as single switch topology is adopted and ZVS Condition is attained. The results of the experiment and the simulation are both validated to assess the performance of the proposed converter.Based on simulation results, the FOPID Controller is utilised to improve dynamic behaviour and is shown to be effective. A 100W universal hardware prototype has been used to develop, implement, and test the proposed converter. 90.9% is the calculated peak efficiency. The proposed control approach and ideal design are demonstrated by an experimental waveform. The following list highlights the converter’s overall advantages. (a) it has a greater voltage gain with higher efficiency (b) switching and conduction losses are less In comparison to current topologies, the proposed IBFC topology results are competitive in terms of cost and efficiency. The proposed converter’s obtained full load efficiency of 90.9% makes it a desirable alternative for PV applications.
TI - Design and implementation of single switch integrated boost and flyback converter for renewable and sustainable energy
JO - PLoS ONE
DO - 10.1371/journal.pone.0287770
DA - 2023-06-30
UR - https://www.deepdyve.com/lp/public-library-of-science-plos-journal/design-and-implementation-of-single-switch-integrated-boost-and-0h3RsHcJdr
SP - e0287770
VL - 18
IS - 6
DP - DeepDyve
ER -