TY - JOUR
AU1 - Chen, Guoqiang
AU2 - Zhang, Junling
AU3 - Wang, Pan
AU4 - Zhou, Jie
AU5 - Gao, Lei
AU6 - Ding, Ruijun
AB - HgCdTe electron injection avalanche photodiodes (e-APDs) work at linear mode. A weak optical current signal is amplified orders of magnitude due to the internal avalanche mechanism and it has been demonstrated to be one of the most promising methods to focal-plane arrays (FPAs) for low-flux like hyper-spectral imaging and high-speed applications such as active imaging. This paper presents the design of a column-shared ADC for cooled e-APDs FPA. Designing a digital FPA requires fulfilling very stringent requirements in terms of power consumption, silicon area and speed. Among the various ADC architectures sigma-delta conversion is a promising solution for high-performance and medium size FPA such as 128×128. The performance of Sigma-delta ADC rather relies on the modulator structure which set over-sampling and noise shaping characteristics than on critical analog circuits. This makes them quite robust and flexible. A multistage noise shaping (MASH) 2-1 single bit architecture sigma-delta conversion with switched-capacitor circuits is designed for column-shared ADC, which is implanted in the GLOBALFOUNDRIES 0.35um CMOS process with 4-poly and 4-metal on the basis of a 100um pixel pitch. It operates under 3.3V supply and the output range of the quantizer is 2V. A quantization noise subtraction circuit in modulator is designed to subtract the quantization noise of first-stage modulator. The quantization noise of the modulator is shaped by a high-pass filter. The silicon area and power consumption are mainly determined by the decimation low pass filter. A cascaded integrator-comb (CIC) filter is designed as the digital decimator filter. CIC filter requires no multipliers and use limited storage thereby leading to more economical hardware implementation. The register word length of the filter in each stage is carefully dimensioned in order to minimize the required hardware. Furthermore, the digital filters operate with a reduced supply voltage to 1.5V. Simulation results show that the modulator achieves the resolution higher than 12bits and 2.4mW power consumption per ADC at 7.7k Samples/s rate.
TI - ROIC with on-chip sigma-delta AD converter for HgCdTe e-APD FPA
JF - Proceedings of SPIE
DO - 10.1117/12.2035479
DA - 2013-10-10
UR - https://www.deepdyve.com/lp/spie/roic-with-on-chip-sigma-delta-ad-converter-for-hgcdte-e-apd-fpa-0PJoilhMV5
SP - 89163B
EP - 89163B-10
VL - 8916
IS - 
DP - DeepDyve
ER -