%0 Journal Article
%T VHDL-based parameterized clock manager simulator for FPGA
%A Pozniak, Krzysztof T.
%J Proceedings of SPIE
%V 10808
%P 108083Y-108083Y-10
%@ 0277-786X
%D 2018-10-01
%I SPIE
%~ DeepDyve