%0 Journal Article
%T Bulk planar 20nm high-k/metal gate CMOS technology platform for low power and high performance applications
%A Cho, H.-J.
%A Seo, K.-I.
%A Jeong, W.C.
%A Kim, Y.-H.
%A Lim, Y.D.
%A Jang, W.W.
%A Hong, J.G.
%A Suk, S.D.
%A Li, M.
%A Ryou, C.
%A Rhee, H.S.
%A Lee, J.G.
%A Kang, H.S.
%A Son, Y.S.
%A Cheng, C.L.
%A Hong, S.H.
%A Yang, W.S.
%A Nam, S.W.
%A Ahn, J.H.
%A Lee, D.H.
%A Park, S.
%A Sadaaki, M.
%A Cha, D.H.
%A Kim, D.W.
%A Sim, S.P.
%A Hyun, S.
%A Koh, C.G.
%A Lee, B.C.
%A Lee, S.G.
%A Kim, M.C.
%A Bae, Y.K.
%A Yoon, B.
%A Kang, S.B.
%A Hong, J.S.
%A Choi, S.
%A Sohn, D.K.
%A Yoon, J. S.
%A Chung, C.
%A ,
%J 2011 International Electron Devices Meeting
%D 2011-12-01
%I IEEE
%~ DeepDyve