%0 Journal Article
%T Layout induced variability and manufacturability checks in FinFETs process
%A Ban, Yongchan
%A Sweis, Jason
%A Hurat, Philippe
%A Lai, Ya-Chieh
%A Kang, Yongseok
%A Paik, Woo Hyun
%A Xu, Wei
%A Song, Huiyuan
%J Proceedings of SPIE
%V 9053
%P 90530I-90530I-7
%@ 0277-786X
%D 2014-03-28
%I SPIE
%~ DeepDyve