%0 Journal Article
%T Demonstration of Yield Improvement for On-Via MTJ Using a 2-Mbit 1T-1MTJ STT-MRAM Test Chip
%A Koike, Hiroki
%A Miura, Sadahiko
%A Honjo, Hiroaki
%A Watanabe, Toshinari
%A Sato, Hideo
%A Sato, Soshi
%A Nasuno, Takashi
%A Noguchi, Yasuo
%A Yasuhira, Mitsuo
%A Tanigawa, Takaho
%A Muraguchi, Masakazu
%A Niwa, Masaaki
%A Ito, Kenchi
%A Ikeda, Shoji
%A Ohno, Hideo
%A Endoh, Tetsuo
%A ,
%J 2016 IEEE 8th International Memory Workshop (IMW)
%D 2016-05-01
%I IEEE
%~ DeepDyve