%0 Journal Article
%T A low-jitter third-order self-biased PLL with adaptive fast-locking scheme for SerDes interfaces
%A Zhang, Hong
%A Du, Xin
%A Zhang, Yao
%A Gong, Liao
%A Cheng, Jun
%J Analog Integrated Circuits and Signal Processing
%V 85
%N 2
%P 311-321
%@ 0925-1030
%D 2015-08-04
%I Springer US
%~ DeepDyve