%0 Journal Article
%T Performance-binning and yield-improvement by clock-edge adjusted circuit for multi-Vdd multi-Vth designed chips
%A Cheng, Ching-Hwa
%J Analog Integrated Circuits and Signal Processing
%V 109
%N 3
%P 535-544
%@ 0925-1030
%D 2021-12-01
%I Springer US
%~ DeepDyve