%0 Journal Article
%T The Power Efficient Ternary Logic Half Adder and Multiplier Designs Using the GNRFET Technology
%A Mahesh, Kuruva
%A Shameem, Syed
%J Transactions on Electrical and Electronic Materials
%V OnlineFirst
%P 1-16
%@ 1229-7607
%D 2025-05-08
%I The Korean Institute of Electrical and Electronic Material Engineers (KIEEME)
%~ DeepDyve