%0 Journal Article
%T FPGA design and implementation of TRNG architecture using ADPLL based on fir as loop filter
%A Meitei, Huirem Bharat
%A Kumar, Manoj
%J Analog Integrated Circuits and Signal Processing
%V 122
%N 1
%@ 0925-1030
%D 2025-01-01
%I Springer US
%~ DeepDyve