%0 Journal Article
%T Timing-Driven Simulated Annealing for FPGA Placement in Neural Network Realization
%A Yu, Le
%A Guo, Baojin
%J Electronics
%V 12
%N 17
%@ 2079-9292
%D 2023-08-23
%I Multidisciplinary Digital Publishing Institute
%~ DeepDyve