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Hierarchical synthesis system with hybrid DLO‐MOGA optimization

Hierarchical synthesis system with hybrid DLO‐MOGA optimization Purpose – The purpose of this paper is to present a hierarchical circuit synthesis system with a hybrid deterministic local optimization – multi‐objective genetic algorithm (DLO‐MOGA) optimization scheme for system‐level synthesis. Design/methodology/approach – The use of a local optimization with a deterministic algorithm based on linear equations which is computationally efficient and improves the feasibility of designs, allows reduction in the number of MOGA generations required to achieve convergence. Findings – This approach reduces the total number of simulation iterations required for optimization. Reduction in run time enables use of full transistor‐level models for simulation of critical system‐level sub‐blocks. Consequently, for system‐level synthesis, simulation accuracy is maintained. The approach is demonstrated for the design of pipeline analog‐to‐digital converters on a 0.35 μm process. Originality/value – The use of a hybrid DLO‐MOGA optimization approach is a new approach to improve hierarchical circuit synthesis time while preserving accuracy. http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png COMPEL: The International Journal for Computation and Mathematics in Electrical and Electronic Engineering Emerald Publishing

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References (31)

Publisher
Emerald Publishing
Copyright
Copyright © 2011 Emerald Group Publishing Limited. All rights reserved.
ISSN
0332-1649
DOI
10.1108/03321641111101186
Publisher site
See Article on Publisher Site

Abstract

Purpose – The purpose of this paper is to present a hierarchical circuit synthesis system with a hybrid deterministic local optimization – multi‐objective genetic algorithm (DLO‐MOGA) optimization scheme for system‐level synthesis. Design/methodology/approach – The use of a local optimization with a deterministic algorithm based on linear equations which is computationally efficient and improves the feasibility of designs, allows reduction in the number of MOGA generations required to achieve convergence. Findings – This approach reduces the total number of simulation iterations required for optimization. Reduction in run time enables use of full transistor‐level models for simulation of critical system‐level sub‐blocks. Consequently, for system‐level synthesis, simulation accuracy is maintained. The approach is demonstrated for the design of pipeline analog‐to‐digital converters on a 0.35 μm process. Originality/value – The use of a hybrid DLO‐MOGA optimization approach is a new approach to improve hierarchical circuit synthesis time while preserving accuracy.

Journal

COMPEL: The International Journal for Computation and Mathematics in Electrical and Electronic EngineeringEmerald Publishing

Published: Mar 8, 2011

Keywords: Programming and algorithm theory; Systems and control theory; Control system synthesis

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