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Nano-Subsidence Assisted Precise Integration of Patterned Two-Dimensional Materials for High-Performance Photodetector Arrays

Nano-Subsidence Assisted Precise Integration of Patterned Two-Dimensional Materials for... Published at ACS Nano 13, 2654 (2019), doi: 10.1021/acsnano.9b00889 Nano-Subsidence Assisted Precise Integration of Patterned Two- Dimensional Materials for High-Performance Photodetector Arrays 1,2* 1 1 1 1 Song-Lin Li, Lei Zhang, Xiaolan Zhong, Marco Gobbi, Simone Bertolazzi, Wei 3 3 3 1§ * 1* Guo, Bin Wu, Yunqi Liu, Emanuele Orgiu, Paolo Samorì University of Strasbourg, CNRS, ISIS UMR 7006, 8 allé e Gaspard Monge, F-67000 Strasbourg, France National Laboratory of Solid State Microstructures, School of Electronic Science and Engineering and Collaborative Innovation Center of Advanced Microstructures, Nanjing University, Nanjing 210023, China Beijing National Laboratory for Molecular Sciences, Institute of Chemistry, Chinese Academy of Science, Beijing 10086, China Present address: Institut national de la recherche scientifique (INRS), EMT Center, 1650 Blvd. Lionel-Boulet, J3X 1S2 Varennes, Canada Corresponding Authors E-mail: sli@nju.edu.cn (S.L.L), emanuele.orgiu@emt.inrs.ca (E.O.), samori@unistra.fr (P.S.) 1 Published at ACS Nano 13, 2654 (2019), doi: 10.1021/acsnano.9b00889 ABSTRACT The spatially precise integration of arrays of micro-patterned two-dimensional (2D) crystals onto three-dimensionally structured Si/SiO substrates represents an attractive strategy towards the low-cost system-on-chip integration of extended functions in silicon microelectronics. However, the reliable integration of the arrays of 2D materials on non-flat surfaces has thus far proved extremely challenging due to their poor adhesion to underlying substrates as ruled by weak van der Waals interactions. Here we report on a novel fabrication method based on nano-subsidence which enables the precise and reliable integration of the micro-patterned 2D materials/silicon photodiode arrays exhibiting high uniformity. Our devices display peak sensitivity as high as 0.35 A/W and external quantum efficiency (EQE) of ~90%, outperforming most commercial photodiodes. The nano-subsidence technique opens a viable path to on-chip integrate 2D crystals onto silicon for beyond-silicon microelectronics. 2 Published at ACS Nano 13, 2654 (2019), doi: 10.1021/acsnano.9b00889 MAIN TEXT With Moore’s law reaching its limit , the semiconductor industry is urgently searching for innovative strategies to go beyond standard microelectronics. One of the most recent and intriguing strategies in modern electronics, referred to as system-on- 2-4 chip (SoC) for more-than-Moore electronics , aims to integrate various active modules in individual chips wherein different functional materials are combined with standard silicon technology. This hybrid approach enables the introduction of extended functionalities such as data storage, sensing, communication and self- powering to conventional logic modules, therefore expanding the current capabilities 5-9 of logic microelectronics. In this context, two-dimensional (2D) atomic crystals , which include a vast library of materials with each one featuring distinctive physical and electronic properties, have emerged as outstanding candidates for integration into silicon to create hybrid devices with unique capabilities . For the purpose of SoC application, different materials are required to be hetero- integrated onto silicon through direct contact or interconnection . Previous reports revealed that 2D crystals could be directly transferred onto three-dimensionally 11-13 14-16 17 structured silicon for energy harvesting , photonics , and electronics , providing evidence for their potential as on-chip functional modules. However, in such experiments the cumbersome fabrication process following the 2D crystal transfer needs to be minimized, since the atomically thin 2D crystals are prone to shear from or even to come off the substrate during microfabrication processing such as photoresist deposition and pattern development. These fabrication issues severely hamper the applicability of patterning large 2D sheets into micrometric functional arrays as active SoC components. For these reasons, to date such hybrid devices are mostly restricted to large 2D sheets forming individual active units; the precise and stable integration of arrays of micro-patterned 2D crystals for advanced electronics has remained elusive. Here, we have devised a nano-subsidence integration method which enables spatially precise and high-yield integration of arrays of micro-patterned 2D crystals onto a three-dimensional substrate such as a patterned Si/SiO surface. Such method enables the fabrication of high performance arrays of photodetectors. As a proof of concept, 2 × 2 type four-quadrant 2D crystal/silicon diodes used as photodetectors are demonstrated. By engineering the optical antireflection and graphene work function, our photodetectors exhibit remarkably high peak sensitivity up to 0.35 A/W and EQE of ~90% at 480 nm, as well as high spatial uniformity. 3 Published at ACS Nano 13, 2654 (2019), doi: 10.1021/acsnano.9b00889 Depending on the optical wavelength range, the overall system performances are comparable to or higher than those of commercial silicon diode-based photodetectors. The conventional method for integrating 2D crystals into silicon-based technology consists in their direct transfer onto three-dimensionally predefined Si/SiO 11-15,17,18 substrates , as portrayed in Fig. 1a. In this approach, the SiO capping above silicon is used as both sacrificing and insulating layers. Selected SiO sacrificing areas are pre-etched to open a window, which allows direct contact between the 2D crystals and underlying silicon, serving as active functional region; the rest SiO areas around the window work as insulating layers for external wiring, resulting in stepwise substrate surfaces . When 2D crystals are transferred over patterned surfaces, they have to physically adapt to the patterns in relief. Since the 2D crystals cannot uniformly land on the top part(s) of the relief(s) and on the surface during a mechanical transfer process, the poor adhesion between 2D crystals and the substrate 20,21 leads to the emergence of physical corrugations and bubbles . In turn, such weak substrate adhesion causes the sliding off or even removal of 2D crystals in the subsequent lithography processing necessary for patterning the 2D crystals or defining microelectrodes. Moreover, it is extremely challenging to precisely align all the micrometric 2D crystals at the desired positions on pre-patterned substrates, as it relies on manual alignment and operation under optical microscope, where location uncertainty is within several micrometers . Thus, by employing a conventional method, it is almost impossible to integrate arrays of micrometric 2D crystals onto three-dimensional substrates with spatial precision and at high yield. To address the above-mentioned challenges, we have conceived the nano- subsidence integration method that allows a high-yield hetero-integration (Fig. 1b). The method relies on the metallization before the 2D crystal patterning and SiO etching, in order to use the solid electrodes as anchoring bars to prevent the 2D crystals from shearing during the following processing. The alignment among 2D crystals, electrodes, and step edges can then be accurately defined through photolithography, ensuring high spatial precision in the hetero-integration. The third consideration is to etch the SiO sacrificing areas in the last fabrication step and the arrays of micro-patterned 2D crystals can gently subside, taking advantage of the flexibility of the ultrathin 2D crystals, and adapt to the stepwise substrates with negligible strain and improved adhesion. As an additional benefit, the formation of hetero-junctions between 2D crystals and silicon takes place in the last step, avoiding 4 Published at ACS Nano 13, 2654 (2019), doi: 10.1021/acsnano.9b00889 exposure of the fresh silicon surface to air thereby avoiding any environmental contamination. Figure 1c sketches the individual processing steps of the novel integration technique while showing corresponding optical microscopy images. First, the large- area CVD graphene is transferred onto a flat SiO /Si substrate. Graphene adheres well to the substrate thanks to the large contact area and the superior flatness of the pristine SiO surface. Metal electrodes with a given pattern are then deposited onto graphene through a standard photolithographic process followed by thermal evaporation of the metal and a lift-off step. Afterwards, graphene is patterned through photolithography and oxygen plasma etching. Finally, the SiO layer in the device active region is wet etched via a photoresist mask, so that the graphene layers gently fall down and make contact to the exposed silicon. After thoroughly rinsing in deionized water, the samples are dried out in vacuum to desorb the encapsulated water between graphene and silicon. By means of the capillary action formed during the vacuum evaporation of the encapsulated water, the graphene is in conformal contact with silicon. We found that the crystal/silicon adhesion is readily wetting-enhanced and is much superior to that formed in the simple dry transfer. As a proof of concept, we apply this method to demonstrate a four-quadrant graphene/silicon photodiode detector, a typical beam position sensing module widely used as collimators and many other adjustment sensors in fiber communication and 22-24 space guidance . The yield of the subsidence integration of graphene to silicon was considerably high: 34 out of 36 quadrants were attained without obvious breaking or folding of graphene, thereby attesting a yield as high as 94 % (supplementary Fig. S2). We note that our approach is extremely versatile and the prototypical 2×2 array fabricated here (Fig. 1c) can be easily upgraded into more complicated arrays/devices. Alongside the use of a novel integration method, we have paid particular attention towards the engineering energy levels of graphene which is known to be essential for 11,13 attaining high photosensing performance . Figure 2a depicts the energy level alignment and working principle of the graphene/silicon photodiodes. The electron- hole pairs are first generated by light irradiation on silicon; then holes drift into graphene assisted by the built-in electric field at the graphene/silicon interface. Hence, the built-in electric field is the driving force for carrier separation and a high built-in electric field would be favorable for this process. In addition, a large interfacial 5 Published at ACS Nano 13, 2654 (2019), doi: 10.1021/acsnano.9b00889 barrier helps to block the drift of electrons to graphene, reducing the carrier recombination in graphene. 25 2 -1 -1 A high-quality CVD graphene with an intrinsic carrier mobility of 2800 cm V s (supplementary Fig. S3d) was used in this work. To increase the interfacial barrier, we implement p-type doping of graphene via spin-coating a thin layer of bis(trifluoromethanesulfonyl)amide (TFSA, [CF SO ] NH, inset of Fig. 2b), a strong 3 2 2 13,26 electron-withdrawing molecule . In contrast to the weak doping effect by ambient oxygen and water molecules with a shift of charge neutrality point of 17 V (supplementary Fig. S3a), the TFSA doping determines a larger shift of ~270 V (supplementary Fig. S4c). Such a large shift corresponds to a rather high surface 13 -2 doping concentration of 6.5×10 cm and a work function increase of 0.75 eV in graphene, as estimated through the equation 𝜀 = ℏ ∙ 𝑣 ∙ , where 𝜀 , 𝑣 , 𝑛 , and ℏ F F F F denote Fermi energy, Fermi velocity, carrier concentration, and reduced Planck constant, respectively. The strong doping caused an effective interfacial barrier of 0.79 eV (supplementary Fig. S8d). Accordingly, improved photovoltaic behavior was achieved, as confirmed in Fig. 2b by the current-voltage (I-V) characteristics of the pristine and doped devices. TFSA-doped devices exhibited highly enhanced open- circuit voltage (V ), short-circuit current (I ), and fill factor (FF), indicating the OC SC critical role of the interfacial barrier on the photovoltaic performance. In Fig. 2c, we analyzed the I-V behavior of the doped device under dark condition, which reveals a good ideality factor of 2.02 and a high rectification ratio of 10 in the bias range of ±1 V, suggesting an excellent photodiode junction quality. The excellent junction quality is also corroborated by the photovoltaic tests. Before antireflection coating, the doped device shows high photovoltaic efficiencies of 10.1% and 9.1% under 520 nm/43.5 -2 mW· cm and AM1.5 conditions, respectively (supplementary Fig. S10 a and c), 11-13 consistent with the literature results. The series resistance (R ) value was 2 2 estimated to be 0.26 Ω/cm for the 100×100 μm device, which outperforms that of previous reports with device fabricated by direct transfer . We have also measured the response speed of the photodiode under a monochromatic light source. Figure 2d shows a diagram of the piezoelectrically controlled monochromator used in our experiments. The angle of the incoming light from the Xenon lamp is fixed while the angle of reflection beam and the resulting wavelength of the outcoming beam through the slit would change upon piezoelectrical 𝜋𝑛 Published at ACS Nano 13, 2654 (2019), doi: 10.1021/acsnano.9b00889 rotation of the optical grating. Since the light power varies with wavelength (the characteristic spectrum of the system is given in supplementary Fig. S11), a modulated photoelectric response would be observed with changing the optical wavelength. Figure 2e displays the modulated photocurrent modes when the incident light wavelength changes from 500 nm to 300, 350, 400 and 450 nm, respectively. At shorter time scales (Fig. 2f) both the rise and decay time are within 500 μs, which represents the fastest signal that can be detected through our experimental setup limited by the millisecond-scale piezoelectric response rate of the grating driver. Hence, the response speed of our devices, of at least 500 μs, certainly represents an underestimate. Generally, the response time would be longer if the density of interfacial states and charge trapping centers were sizeable. The fast response featured by the devices made with our nano-subsidence method suggests that the graphene/silicon interface of the photodiodes is of high quality. In order to further optimize the performances of our photodiodes, we have employed a surface antireflection capping. This is commonly employed to increase the optical absorption of photodiodes by depositing single or multiple optically 11,28-31 transparent antireflection dielectrics . According to the principle of optical destructive coherence, the reflection rate for a certain light will be minimized when a single antireflective capping layer satisfies the double conditions that 𝑛 = √𝑛 𝑛 𝑟𝑎𝑖 and 𝑑 = 𝜆 /4𝑛 , where 𝑛 , 𝑛 , and 𝑛 are the refractive indices of the 𝑟𝑎𝑖 antireflective capping layer, air and silicon, respectively, and 𝑑 and 𝜆 are the thickness of the capping layer and the incident light wavelength. Given the atomic thickness of the 2D layers and the low formation energies of lattice defects that make 32-34 them prone to damages generated by external high-energy atoms, capping layers grown via aggressive deposition methods (e.g. sputtering) should be avoided. 30,31 Towards this end, we have used thermally evaporated MoO as the capping layer, and the damage to 2D layers are expected to be minimized. The values of 𝑛 are 𝑂𝑀𝑜 3 close to those of 𝑛 𝑛 in most range of visible light (supplementary Fig. S6), 𝑟𝑎𝑖 suggesting that it is a suitable antireflection material. By theoretical calculations, we also confirmed that the effect of graphene on optical absorption is negligible due to its atomic thickness (supplementary Fig. S7). Figure 3a sketches the device cross section of pristine versus capped devices and their related optical images. Micro-area reflection measurement revealed that the 𝑠𝑖 𝐴𝑅 𝑠𝑖 𝐴𝑅 𝐴𝑅 𝐴𝑅 𝑠𝑖 𝐴𝑅 Published at ACS Nano 13, 2654 (2019), doi: 10.1021/acsnano.9b00889 reflectivity is remarkably reduced from 36% to 8% at  = 520 nm upon the use of a capping layer of 55-nm MoO . The reduction of the optical reflection is also corroborated by the difference in brightness of the optical images of the pristine and capped silicon/graphene stacks, where a lower brightness is observed in the latter (around orange dot in the lower panels of Fig. 3a). As a result, the photoresponse of the devices is enhanced. Under 43.5 mW/cm illumination at 520 nm, the photocurrent increases from 11.6 to 16.7 mA/cm (Fig. 3b). The effect of the MoO3 antireflective capping is further analyzed by correlating micro-area reflection spectra to the external 𝐽 ħ𝐶 𝑝 ℎ quantum efficiency (EQE) of our devices. Here EQE is estimated by EQE = 𝑒𝑃𝜆 where 𝐽 is the photocurrent density, C is the speed of light within vacuum, 𝑒 is the 𝑝 ℎ elementary charge, P is the light power. The EQE data was extracted from the photocurrent spectrum recorded between 320 to 690 nm. The open blue and red circles in Fig. 3c compare the EQE before and after deposition of a 55-nm-MoO capping layer. As expected, the capping enhances (or reduces) the EQE around  = 480 (or  = 320 nm), in agreement with the interference conditions at the corresponding wavelengths (supplementary Fig. S7c). In Fig. 3c, we also compare the EQE with device absorption rate (1-R, with R the reflectivity) as measured by micro- area reflection. The EQE lines follow closely with the absorption rates, suggesting a near-unity internal quantum efficiency (IQE) since IQE=EQE/(1-R). In the experiments, the peak IQE reaches 90% at 480 nm, approaching the ideal unitary IQE of the photodiodes . The ~10% reduction to the ideal values (supplementary Fig. S7, c and d) stems likely from local variations of refractive index in the MoO capping layer caused by the presence of pinholes or oxygen loss. The extremely high IEQ achieved here corroborates again the high integration quality of the arrays via our nano-subsidence method. The photocurrent properties of the capped devices were extensively characterized by varying the optical wavelength and power. Figure 3d plots the photoelectric sensitivity versus the two parameters of light wavelength and power. Despite of strong dependence on light wavelength, the sensitivity is basically power independent within the measurement range of optical power (from 10% to 100%) since the devices show negligible saturation in photoresponse below 100% power (Fig. 3e). To evaluate the potential of the nano-subsided photodiodes as a system-on-chip module, we also compare the EQE of our devices in Fig. 3f and Table 1 with currently commercial 8 Published at ACS Nano 13, 2654 (2019), doi: 10.1021/acsnano.9b00889 photodiodes based on silicon pn junctions (ThorLabs FDS010 and FDS10×10, Hamamatsu S1336BQ). Remarkably, our devices are superior to their commercial counterparts in the visible region from 400 to 700 nm, therefore representing a prototypical high-performance system-on-chip module for the beyond-silicon circuitry. To assess the photoresponse uniformity of individual array units, we mounted our samples onto a test printed circuit board (PCB) (Fig. 4a). In order to have a reliable (wire) bonding to device electrodes, no MoO capping layer is deposited in this test. Figures 4b and 4c show enlarged images on local arrays at different magnification ratios where multiple quadrant photodiodes were prepared. During testing, each unit was exposed to a 532-nm focused laser beam with a power of about 10 W/cm . Figures 4d-4f show the corresponding photoelectric curves. Almost identical I-V curves were recorded for the four units, with I =0.56±0.08 μA. A slight degradation SC of the fill factor was observed in all the four I-V curves, which is likely due to the effect of ambient moisture on the hygroscopic dopant TFSA during the measurements. Finally, we have verified the generalization of the nano-subsidence assisted integration method by replacing graphene with another renowned 2D crystal, i.e. molybdenum disulfide (MoS ). Figure 5a shows the optical images of a MoS /silicon 2 2 junction before and after SiO etching. A mechanically exfoliated 5-layer-thick MoS 2 2 was used in this device. Since MoS is normally slightly n-doped, the MoS /silicon 2 2 ++ stack can be regarded as an n/n homo-junction with relatively small barrier heights . Figure 5b shows a corresponding band diagram, where Φ and Φ are the barriers C V for blocking the reverse motions of electrons and holes at the conduction and valence bands, respectively. Owing to smaller Φ and Φ as compared to the case of doped C V graphene/silicon (Fig. 2a), a large number of carriers can drift and recombine, resulting in lower V and J (Fig. 5c) and a reduced fill factor (Fig. 5d). However, OC SC in spite of the degraded photoelectric properties with respect to graphene/silicon junctions, the MoS /silicon junction still exhibited a photoelectric behavior similar to that of small-barrier diodes in which backward current is enhanced and reasonably high other photoelectric parameters. In particular, a large rectification ratio of 10 within ±1 V (Fig. 5c), notable photoelectric behavior (Figs. 5c and 5d), reasonably high peak EQE of ~25% (Fig. 5g), and fast photoresponse of 1 ms (Fig. 5h) are measured. 9 Published at ACS Nano 13, 2654 (2019), doi: 10.1021/acsnano.9b00889 In conclusion, we have developed a novel method enabling the integration of atomically thin 2D crystals for the system-on-chip electronics, through the precise location of ultrathin crystals and on-chip integration of arrays of micro-patterned 2D crystals with a minimized residual strain of the 2D crystals on non-flat substrates. Noteworthy, this integration method combines several advantages. First, the substrate surface was kept flat in all photolithography steps (i.e., metallization, patterning 2D crystals, and defining mask for SiO etching), which facilitates the microfabrication processing such as resist coating. Second, high-yield integration of 2D crystals into the stepwise substrate was realized via controlled gentle subsidence assisted by capillary forces during vacuum dry, which also ensures a precise positioning and alignment of the micrometric 2D crystals onto the target electrodes. Third, the exposure of bare silicon surface to air is minimized, resulting in a high quality of the 2D material/Si interface which, as a result, improves the junction performances. Taking graphene and MoS as model systems, we demonstrated the general applicability of such unique integration method to integrate all kinds of 2D crystals onto silicon as photodiodes. The photodetector performances surpass those of commercial photodiodes after appropriate device optimization. Not limited to the photoelectric function and materials demonstrated above, the concept of subsidence integration via an underlying sacrificial layer could also be extended to wider applications, such as 3D interconnection, optical waveguides, and microfluidic channels, and hence it holds great potential for realizing more versatile modules for the beyond-silicon more-than-Moore microelectronics. Acknowledgments We acknowledge funding from the European Commission through the Graphene Flagship (GA-696656), the FET project UPGRADE (GA-309056) and Marie-Curie IEF MULTI2DSWITCH (GA-700802), the M-ERA.NET project MODIGLIANI, the Agence Nationale de la Recherche through the Labex projects CSC (ANR-10-LABX- 0026 CSC) and Nanostructures in Interaction with their Environment (ANR-11- LABX-0058 NIE) within the Investissement d’Avenir program (ANR-10-120 IDEX- 0002-02), and the International Center for Frontier Research in Chemistry (icFRC). This project is also partially supported by the National Key R&D Program of China (2017YFA0206304) and the National Natural Science Foundation of China (61674080). 10 Published at ACS Nano 13, 2654 (2019), doi: 10.1021/acsnano.9b00889 Author contributions S.L.L., E.O. and P.S. conceived the experiment and designed the study. S.L.L. performed the experiments and developed the fabrication method. W.G., B.W, and Y.L. synthesized and provided the CVD graphene sample. S.L.L., E.O. and P.S. co- wrote the paper. All authors discussed the results and contributed to the interpretation of data, as well as contributing to editing the manuscript. Additional information Supplementary information is available in the online version of the paper. Reprints and permissions information is available online at www.nature.com/reprints. Correspondence and requests for materials should be addressed to S.L.L., E.O. and P.S. Competing financial interests The authors declare no competing financial interests. Table 1 Comparison of EQE performance of nano-subsidence fabricated graphene/silicon photodiode with typical commercial silicon photodiodes at different wavelength values. The values in parentheses show the EQE difference of the commercial devices as compared to our graphene/silicon device. EQE EQE EQE EQE EQE Photodiode @ 350 nm @ 450 nm @ 500 nm @ 550 nm @ 650 nm This work 27.2% 84.2% 90.3% 89.0% 86.2% ThorLabs 58.9% 68.6% 73.6% 76.5% 79.0% FDS10×10 (+117%) (-19%) (-18%) (-14%) (-18%) (UV enhanced) Hamamatsu 56.1% 60.8% 63.7% 65.7% 67.5% S1336BQ (+106%) (-28%) (-29%) (-26%) (-22%) (UV enhanced) ThorLabs 19.0% 40.8% 54.2% 64.5% 76.8% FDS010 (-30%) (-52%) (-40%) (-28%) (-11%) 11 Published at ACS Nano 13, 2654 (2019), doi: 10.1021/acsnano.9b00889 Methods Transfer of CVD graphene on flat SiO /Si substrates. Large-area high-quality monolayer graphene was grown on 25 μm thick copper foils by CVD . A 20 mg/mL PMMA/chlorobenzene solution was spin-coated on the graphene/copper foils at 3000 rpm for 30 s, which was then heated dry on a hot plate at 180 ° C for 1 minute. A PDMS scaffold with a hole of ~10 mm in diameter was gently pressed down onto the PMMA/graphene/copper stacks, with the PDMS scaffold attaching to the stacks. Afterward, the whole stack was placed floating on an ammonium persulfate (0.1 M) solution with the copper face downwards to etch the copper foil. After removing the copper foils, the PDMS/PMMA/graphene stack was rinsed in distilled water for several times and was finally scooped out by a flat SiO /Si substrate. The silicon wafers (from IPMS Fraunhofer Institute, Dresden) were capped with a 90-nm-thick thermally grown SiO dielectric layer and were n-doped to a high level of ∼3 × 10 −3 cm . Device fabrication. Optical lithography was performed through a direct laser writing system (LW405B, Microtech Inc.). A thin positive photoresist AZ1505 was used as a mask for graphene patterning and metallization. The exposure resolution is about 1 μm. AZ 726 metal- ion free developer and dimethyl sulfoxide were used for resist development and lift- off, respectively. To increase the adhesion ability of resist and development, the surface of silicon wafers was modified by thermally evaporated hexamethyldisilazane molecules before applying the resist. The SiO dielectric layers were etched by standard buffered HF etchant (NH F : HF = 6 : 1). The electrodes were realized by thermal evaporation of 1 nm of chromium and 50 nm of gold. The use of chromium adhesion layer is necessary in order to prevent the unwanted lateral etching the SiO underneath electrodes (See also supplementary Fig. S1). Characterization and measurements. All optical images of graphene and devices were taken with an Olympus BX53M microscope. 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V., Two-Dimensional MoS under Ion Irradiation: From Controlled Defect Production to Electronic Structure Engineering. 2D Mater. 2017, 4, 025078. 16 Figure TOC Light Bias For Table of Contents Only Figure 1 Light a b 2D crystal Bias 30/2 nm Electrode Electrode direct Electrode Etching X nm 2D crystal 2D crystal transfer G/Si junction SiO + 230 nm Insulating SiO 2 A SiO 2 + + - - - Si 650 mm Si Heavily doped Si c Nano-subsidence integration Metallization Graphene patterning SiO etching SiO Q2 Q1 CVD graphene Q3 Q4 100μm 20μm 20μm 20μm Figure 1 Schematic diagrams of hybrid integration by conventional direct transfer and our nano-subsidence techniques. a, Cross-sectional diagram for the conventional direct transfer integration, which features several risks of tearing out and sliding off when the sizes of 2D crystals are small, due to the weak stickability of 2D crystals and the presence of stepwise substrate structure. b, The concept of the improved hybrid integration by nano-subsidence in which the 2D crystals are fixed by using the metallic electrodes as anchoring bars and selectively etching out the sacrificial SiO layer in the last. The hybrid integration is completed after the gentle subsidence of 2D crystals. c, The processing flow and corresponding images for each critical integration step for the subsidence integration. Its processing sequence is renewed to transfer- metallization-patterning-etching to ensure the precise location of 2D crystals. Figure 2 a b c -8 520 nm Ideality factor 44.8 mW/cm =2.02 0.01 Light -9 n-doped Si exp. Graphene Pristine fit 10 520 nm -10 - - 7 5 -2 10 -6 10 + -11 E + Dark -6 TFSA doped -1 0 1 -12 Bias (V) -12 0.0 0.2 0.4 0.6 0.0 0.2 0.4 0.6 Bias (V) Bias (V) d e f 500 nm white light 500 ms 500 ms rotate 500 nm 450 nm optical slit grating 400 nm 4 350 nm 350 nm photodiode 300 nm 5 6 23 24 0 20 40 60 Time (ms) Time (ms) Figure 2 Photoelectric properties of hybrid graphene/silicon diodes prepared by the nano- subsidence integration. a, Diagram of the energy level alignment and operation principle of the graphene/silicon photodiodes. b, Comparative photoelectric behavior of the photodiodes before and after engineering band alignment via TFSA doping. Inset: The molecular structure of TFSA and the change of Fermi level of graphene before and after TFSA doping. c, Fitting of I-V curve under dark condition to extract the ideality factor of the diodes. Inset: Semi-logarithmic plot of the I-V curves under both dark and light conditions. High rectification and zero-bias signal-noise ratios 5 7 of 10 and 10 are observed. d, Principle of wavelength scan for characterizing photoresponse time, where the piezoelectric response time is below the order of ms that defines the lower limit of our samples. e, Modulation of photocurrent by varying the excitation wavelength. f, Enlarged figure to analyze the rise and decay times of our photodiodes which are estimated to be better than 500 μs. J (mA/cm ) Photocurrent (0.1 mA) I (A) Photocurrent (0.1 mA) J (mA/cm ) Figure 3 a b c 8% 100 36% 520 nm AR layer 2 No AR layer 43.5 mW/cm MoO AR 55nm MoO Graphene/TFSA Graphene/TFSA Si Si wo. MoO AR -6 wo. MoO AR -12 1-R EQE MoO AR Si/G Si/G/MoO -18 300 400 500 600 700 800 0.0 0.2 0.4 0.6 SiO SiO /MoO 2 3 Bias (V) Wavelegnth (nm) d e f 0.5 Sensitivity (A/W) This work 650 nm Si/G/MoO 0.4 0.48 550 nm 0.36 0.3 450 nm 0.24 0.2 0.12 Commercial Si diode 0.1 350 nm ThorLabs_FDS10x10 0.00 Hamamatsu_S1336BQ ThorLabs_FDS010 0.0 0 20 40 60 80 100 0 20 40 60 80 100 300 400 500 600 700 Light power (%) Light power (%) Wavelength (nm) Figure 3 Photoelectric properties of graphene/silicon diodes after capping antireflective MoO . a, Cross-sectional diagrams and optical images of the pristine and MoO capped devices. 3 3 b, Comparative I-V behavior of the photodiodes before (blue) and after (red) capping 55 nm MoO antireflective layers. The photocurrent increases from 12 to 17 mA/cm . c, Comparison of absorption rate (1-R, lines) and external quantum efficiency (EQE, open dots) before (blue) and after (red) MoO capping. d, Contour plot of photoelectric sensitivity versus wavelength and light power. e, Sensitivity as a function of light power at different wavelength values from 350 to 650 nm. The devices show negligible saturation in photoresponse within experimental power range of ~50 mW/cm . f, Comparison of EQE with three typical commercial silicon photodiodes. Our devices (red dots) rivals the counterparts in the visible regime from 400 to 700 nm after the MoO antireflective capping. Wavelength (nm) Sensitivity (A/W) Current (mA/cm ) 1-R and EQE (%) EQE (%) Figure 4 a b c d 0.0 e 0.0 Quadrant 2 Quadrant 1 -0.2 -0.2 -0.4 -0.4 -0.6 -0.6 -0.6 -0.3 0.0 0.3 0.6 -0.6 -0.3 0.0 0.3 0.6 Vd,V (dataX) Vd,V (dataX) 0.0 0.0 f g Quadrant 3 Quadrant 4 -0.2 -0.2 -0.4 -0.4 -0.6 -0.6 -0.6 -0.3 0.0 0.3 0.6 -0.6 -0.3 0.0 0.3 0.6 Bias (V) Bias (V) Figure 4 Test of the uniformity of array units. a, Optical image of a testing module with samples mounted onto a home-made printed circuit board. b, Enlarged image for a local area with three quadrant arrays. c, Further enlarged image for an individual 2×2 quadrant array. d-g, One- by-one test of the photoelectric behavior for the four array units (i.e., from quadrant 1 to 4). Inset images show the illumination locations of the focused excitation laser. Photocurrent (mA) Photocurrent (mA) Figure 5 Light Si (n-doped) MoS a b -17 -3 N =3x10 cm (pristine) 6μm 6μm - Φ MoS MoS E V + SiO Si c e g 6 Sensitivity (A/W) 5 10 -1 10 0.15 -2 0.12 10 -0.5 0.0 0.5 15 MoS /Si heterojuction 0.09 1 0.06 0.03 Dark 0.00 -1 546 nm 20 40 60 80 100 -2 -1 0 1 2 300 400 500 600 700 Light power (%) Bias (V) Wavelength (nm) d f h 0.15 500 nm 0 650 nm 450 nm 0.10 550 nm MoS /Si 400 nm 450 nm 0.05 350 nm V = 0.2 V OC 350 nm -5 J = 4.7 mA/cm SC 300 nm 0.00 0.0 0.1 0.2 0 20 40 60 80 100 0 50 100 150 Bias (V) Power (%) Time (ms) Figure 5 Test of the feasibility of the subsidence integration technique to other 2D crystals. a, Optical images for a typical MoS /silicon diode before and after SiO etching. b, Diagram of the 2 2 ++ energy level alignment of the MoS /silicon diode, which is actually an n/n heterojunction with small barrier heights (Φ and Φ ). c, Semi-logarithmic plot of the I-V curves under both dark C V (black dots) and light (red circles) conditions. d, Corresponding linear plot of the I-V curve. e, Contour plot of photoelectric sensitivity versus wavelength and light power. f, Sensitivity as a function of light power at different wavelength values from 350 to 650 nm. The devices also show negligible saturation in photoresponse within experimental power range. g, Estimated EQE for different wavelengths from 320 to 700 nm. h, Modulation of photocurrent by varying the excitation wavelength. Current (mA/cm ) Current (mA/cm ) Sensitivity (A/W) Wavelength (nm) Photocurrent (nA) Quantum Efficiency (%) Supporting Information Nano-Subsidence Assisted Precise Integration of Patterned Two-Dimensional Materials for High-Performance Photodetector Arrays *,1,2,5,6 1 1 1 1 Song-Lin Li, Lei Zhang, Xiaolan Zhong, Marco Gobbi, Simone Bertolazzi, 3 3 3 2 4 4,5,6 Wei Guo, Bin Wu, Yunqi Liu, Ning Xu, Weiyu Niu, Yufeng Hao, Emanuele *,1,§ *,1 Orgiu, Paolo Samorì University of Strasbourg, CNRS, ISIS UMR 7006, 8 allée Gaspard Monge, F-67000 Strasbourg, France; School of Electronic Science and Engineering, Nanjing University, Nanjing 210023, China; Beijing National Laboratory for Molecular Sciences, Institute of Chemistry, Chinese Academy of Science, Beijing 10086, China; College of Engineering and Applied Sciences, Nanjing University, Nanjing 210023, China; National Laboratory of Solid State Microstructures, Nanjing University, Nanjing 210093, China; Collaborative Innovation Center of Advanced Microstructures, Nanjing University, Nanjing 210093, China; Present address: Institut national de la recherche scientifique (INRS), EMT Center, 1650 Blvd. Lionel-Boulet, J3X 1S2 Varennes, Canada Address correspondence to sli@nju.edu.cn (S.L.L), emanuele.orgiu@emt.inrs.ca (E.O.), samori@unistra.fr (P.S.) Table of Content 1. Etching rates of SiO at different interfaces S2 2. Nano-subsidence integration S5 3. Intrinsic mobility and contact resistivity of pristine CVD graphene S9 4. Effect of TFSA doping on CVD graphene S11 5. Effect of HNO doping on mechanically exfoliated graphene S12 6. Refractive indices of candidate antireflection capping layers S13 7. Design of MoO antireflection layer S14 8. Effect of barrier height (Φ ) on V S16 B oc 9. Fit of series resistance S17 10. Performance as photovoltaic devices S18 11. Output power and linearity of monochromatic light source S19 S1 1. Etching rates of SiO2 at different interfaces For making 2D flake/Si junction with nano-subsidence method, there are three types of SiO interfaces deserved to consider during the SiO etching: 2D flake/SiO , 2 2 2 electrode/SiO , and resist mask/SiO . The first one is the desired interface for the 2 2 penetration of SiO etchant (BOE solution) to remove the SiO underneath the 2D 2 2 flake, while the latter two are not desired. Hence, the lateral etching rates for the latter two should be minimized. We found that the factor to determine the lateral etching rate of the material/SiO stacks is the chemical bonds formed between the top capping layer and the bottom SiO . In general, the rate is small when there are chemical bonds (Cr/SiO , resist mask/primed SiO ) while it becomes large when no bonds are present 2 2 (graphene/SiO , Au/SiO , resist mask/unprimed SiO ). Since there are no chemical 2 2 2 bonds formed between the 2D flake/SiO stacks, the lateral etching rate is rather large. For the electrode/SiO stacks, an adhesion metal layer such as chromium is very necessary to minim S1: iz e E tth che in g de ra trimenta tes of SiOl a late t difrfa el etc rent in hi te ng rfaces of the SiO under electrodes. Graphene/SiO Au/SiO 2 2 by 2 min. by 2 min. Etched by 2 min. c c' b b' a a' CVDG13_6etch_24.jpg G15H2 1L 5L 40 μm 10 μm 10 μm Resist (Cr)/SiO MS28_dev3_10: Lateral etching by 35 min. Capping layer Etch Cr 35min d d' SiO 3L 1L MS28rmv_J Etched by 1 min. 0.1 e' 10 μm G./SiO2: fast etching rate of 20 μm/min Au/SiO2: fast etching rate of 5 μm/min Cr/SiO2: slow etching rate of 0.08 μm/min 13 μm Figure S1 Etching rates of SiO underneath different capping layers. a-e, Optical images of devices just before SiO etching; a'-e', Corresponding images for devices after etching. The dashed black lines and black arrows indicate the area of graphene and etching directions, respectively. The dashed blue line and blue arrows in panel d' denote the patterned resist windows for etching and the direction of etching progression of the resist mask, respectively. a, graphene capped SiO2; b and c, Au capped SiO2; d and e, resist and Cr capped SiO2. f, Estimated etching rates for SiO2 capped by four types of materials (graphene, Au, mask resist and Cr). Inset: Diagram of lateral etching of SiO underneath a capping layer. Figure S1 shows the results of a comparative experiment where the etching rates of SiO at different interfaces (i.e., graphene/SiO , Au/SiO , resist mask/SiO and 2 2 2 2 S2 Graphene Au Resist Cr Etching rate of SiO (m/min.) 2 Cr/SiO2) are measured. The panels a-e show images of the samples before etching (etching windows to be exposed are visible); the panels a’-e’ show the images after etching. The dashed lines and black arrows indicate the area of graphene and etching directions, respectively. It is well known that there is only simple physical contact (van der Waals interaction) between either graphene or pure gold electrode and SiO (i.e., graphene/SiO and Au/SiO ), where no chemical bonds form, and thus the lateral 2 2 etching rate of SiO is high. Within 2 minutes the etching length could reach as much as 40 and 15 μm at the interfaces of graphene/SiO and Au/SiO , respectively. On the 2 2 contrary, there are strong chemical bonds between Cr and SiO or between resist mask and HMDS primed SiO surface; hence the etching rates for them are as low as ~0.1 and ~0.15 μm/min, respectively. By constant soaking in HF solution of 35 minutes, the etching lengths of SiO are only ~3 and 5.2 μm in cases of Cr and resist mask capping (panels d and d’). Within the normal etching time of about 1.5 min, the unwanted etching lengths are 200-300 nm for the graphene underneath the Au/Cr electrode and resist mask (panels e and e’); the detrimental etching of SiO is negligible. There is also potential risk of formation of low resistive pathways caused by the collapse of the electrode/2D crystal bilayer. However, we found that there is some tolerance in experiment. First, the work function of the Cr/Au electrode (1 nm Cr, 50 nm of Au) is relatively high, mainly following the thick Au layer, and it would form a Schottky junction for the trilayer structure electrode/graphene/n doped silicon. Hence, no obvious low resistive pathway/connection appears even in the event of a small-area bilayer collapse. Second, as an electronic effect of the collapse, the contacting area results in the increase of unfavorable shunt resistance in the circuit loop of photodiodes, which may deform the I-V curve or short-circuit the devices, depending on the magnitude of the shunt resistance. In our experiment, we observed that most devices remain electronically functional with 2-3 μm over etching. The stopping point of etching progression is just the boundary of the 2D crystals, outside which the Cr adhesion layer is strongly bonded to underlying SiO and results in negligible lateral etching rate of this area, as shown by the dashed line in Fig S1 e and e’. Panel f lists the lateral etching rates for the three interfaces. It is shown that the etching rate can vary by 2 orders of magnitude depending on the interface condition i.e., whether chemical bonds can be formed at the interfaces. For instance, depositing S3 Au or graphene onto SiO2 will not create chemical bonds between Au (graphene) and SiO , which results in a high lateral etching rate. Instead, depositing Cr onto SiO 2 2 creates an additional Cr-O bonds (in presence as chromium oxide) between Cr and SiO , which leads to a low lateral etching rate. Since the processing step of SiO 2 2 etching is placed in the last in our nano-subsidence technique, a precise control of the etching rate of SiO is critical for the overall fabrication resolution. We verified that the addition of the adhesion layer (such as Cr, Ti) underneath the metallic electrode, which is translated as an adhesion layer between the electrode and SiO during etching (Figure 1b in the main text), can avoid the unfavorable etching of SiO and hence ensure our fabrication resolution. S4 FigS2: Yield of nano-indentation technique 2. Nano-subsidence integration a b c d e a' b' c' d' e' Q2 Q1 Q2 Q1 Q2 Q1 Q2 Q1 Q2 Q1 Q3 Q3 Q3 Q3 Q4 Q4 Q3 Q4 Q4 Q4 f g h i Good Failed f' g' h' i' Q2 Q1 Q2 Q1 Q2 Q1 Q2 Q1 Q3 Q4 Q3 Q4 Q3 Q3 Q4 40 μm Q4 Figure S2 Yield of device fabricated by the nano-subsidence technique. a-i, Optical images of the four-quadrant photodetector before nano-subsidence; a'-i', Corresponding images for devices after applying the nano-subsidence. The blue and orange dashed lines represent the good and failed quadrants, respectively. Among the 36 quadrants, 34 of them are good. Although slightly fierce operations (such as water scouring to graphene during rinse after HF etching) are employed in sample fabrication, most graphene pieces stick well to the underlying Si layers. Figure S2 show the optical images for the 9 arrays of the four-quadrant devices before and after the subsidence processing. Here, we take one quadrant as an individual sample and the quadrants with visible graphene folding, scrolling or rupture are counted as the failure. We estimated the sample yield as high as 94.4% (34 out of 36 quadrants), which indicates the high reliability of our nano-subsidence technique. By using conventional photolithography, we also fabricated large scale arrays with the nano-subsidence and conventional integration methods, respectively, to enable direct comparison of the two methods. The main results are listed in Table S1 with the superior figures of merit marked in bold. The reported values provide unambiguous evidence that our nano-subsidence integration method outperforms in parameters such as sample yield, probability of strain accumulation, surface roughness of graphene/silicon, and time of air exposure of bare silicon, although both integration S5 methods result in comparable peak photoresponsivity. We have recorded AFM images of the surface following nano-subsidence and conventional integration techniques. The results are displayed in Figure S3 below. We used the root mean square (RMS) roughness in order to gain a quantitative insight into the graphene morphology, and to evaluate the cleanness of the graphene/silicon interfaces. The left panel, displaying devices obtained using our nano-subsidence integration method, reveals a cleaner graphene interface with lower RMS roughness of ~0.52 nm, compared to the right panel which displays interfaces obtained using conventional method, the latter exhibiting a RMS roughness of ~0.84 nm. Table S1 Comparison of different parameters of the two integration methods. Better values are indicated in bold. Nano-subsidence Conventional method method Sample yield ~96% ~88% Probability of strain accumulation <1% >8% Surface roughness of graphene/silicon 0.52 nm 0.84 nm Time of air exposure of bare silicon >3 hours < 60 seconds Peak photoresponsivity 0.35 A/W 0.37 A/W First, the 8% higher yield ratio (96% vs. 88%) is attributed to the effect of electrode anchoring, which stabilizes one of the three edges of the slidable graphene flakes during subsequent microfabricaton processing. Second, the greatly reduced probability of strain accumulation (from 8% to 1%) can be ascribed to the different integration process. In the conventional way, entire pieces of graphene sheets are transferred and closely attached to the whole substrates; no more chance for strain release after heat dry. Instead, in our new technique, the strain accumulated in the first transfer process can be well released in the process of nano-subsidence when SiO is gradually etching way. As mentioned above, except for the anchored edge (Figure 1c, bottom panels), there are two edges of the graphene flakes floated in the etchant and the strain can be well released during the subsidence to bare silicon. Third, the difference in interface cleanness (surface roughness, Figure S3) of graphene/silicon (0.52 vs. 0.84 nm) likely arises from the specific device S6 microstructure as depicted in the cartoon. The devices from nano-subsidence generally feature a less rough underlying support for graphene, which facilitates the expulsion of liquids and soluble impurities during heat/vacuum dry. Instead, the devices fabricated following the conventional method are predefined with silicon cavities, which therefore tend to trap soluble impurities and to contaminate the graphene/silicon interface after heat dry. Trapping of impurities led to an increase of surface roughness. Other bonus from the nano-subsidence technique includes minimized time of air exposure of bare silicon and preserved fresh silicon interface, which offer great flexibility in further interface engineering between silicon and 2D crystals. We also need to clarify the device performance from the two integration techniques, which are comparable, since the peak photoresponsivity reaches 0.35-0.37 A/W when other device parameters are fully optimized. This indicates that the device performance has little to do with the integration methods. Finally, it is worth noting that the yield ratio of the MoS junctions is slightly higher than graphene junctions, reaching nearly 97%, because the MoS flakes adopted are generally thicker and more rigid than graphene, leaving them little chances to rupture. Nano-subsidence integration Conventional integration Heat dry Heat/vacuum dry Graphene Graphene Bare Si Bare Si Liquid expelled Liquid trapped Figure S3 Schematics of formation of interfacial residues between graphene and bare silicon and the corresponding surface roughness of graphene after SiO removal as seen with AFM. Left and right panels are for the nano-subsidence and conventional integration techniques, respectively. S7 Since thick 2D materials would become rigid and unbendable, the conformal step coverage of thick 2D materials on patterned Si substrates would be difficult and there are certain thickness limits for using the nano-subsidence integration. From our data, we can conclude that the lower thickness limit for subsidence integration is 4 layers for graphene and 5 layers for MoS (Figure 5a), respectively. Another factor alleviating the requirement on thickness limit is the gentle slope of ~16° formed at the step, as confirmed by the AFM profile and depicted by the cartoon (Figure S4, right panel). The gentle, rather than sharp, slope normally facilitates the conformal step coverage of 2D films on the patterned steps. Real profile of 2D film 2D film on patterned step Minimized strain Step 84 nm 16° ~300 nm Subsided graphene 84nm Subsided graphene covering patterned step Figure S4 Left: SEM images for junctions with well-subsided graphene. Right: AFM image near a patterned edge of the graphene junction. In both images, no clear traces of strain induced ripples are observed. S8 S3: Intrinsic mobility and contact resistivity of pristine CVD graphene 3. Intrinsic mobility and contact resistivity of pristine CVD graphene 0.6 L = 4.1 m 0.4 V ~ 17 V 10.2 m CNP L = 19.4 m 0.2 0 0.0 -10 0 10 20 30 40 -10 -5 0 5 10 V (V) V (V) g g 1.0  = 2.2 mS, V = 0 2 -1 -1 V = -10 V  = 2800 cm V s 0.8 2 0.6 0.4 V = 10 V 0.2 Pristine 0 0 0.0 0 5 10 15 20 -1 -10 0 -5 -5 0 0 5 5 10 10 V (V) Channel length (m) Figure S5 Extracting intrinsic carrier mobility and contact resistivity of pristine CVD graphene. a, A typical transfer curve of the pristine CVD graphene in air, where the charge neutrality point (V ) is normally at V around 15-17 V. Here the thickness of SiO CNP g 2 dielectric is 90 nm and V = 0.1 V. b, Transfer curves for graphene channels with different ds channel lengths. Inset: Optical image of the device for TLM measurement. c, TLM fit to extract mobility and contact resistance. d, Left axis: Intrinsic transfer curve after ruling out the contact effect, which can be used to extract intrinsic mobility. Right axis: Extracted contact resistivity versus gate voltage. The CVD graphene was grown on copper foils and its quality was carefully checked. The intrinsic carrier mobility and contact resistance were estimated by the conventional transfer-length measurement (TLM). In the ambient environment the graphene is p-doped by oxygen and humidity, which shifts the charge neutrality point (V ) to around V = 15-17 V, as shown in Figure S5a. To estimate the hole (the CNP g leading carriers passing graphene in this study) mobility of the CVD graphene, we used the data in the V range from -10 to 10 V. As shown in the inset of Figure S5b, four electrodes with varied spacing were defined on a well etched graphene ribbon, where three graphene channels were defined with channel lengths (L) of 4.1, 10.2 and 19.4 μm, respectively. Figure S5b shows the transfer curves of the three channels S9 Resistance* Width (cm) Conductance (mS) Conductance (mS) Square conductivity (mS) Contact resistivity (Wcm) where the gate voltage (Vg) is changed from -10 to +10 V. All channels exhibit p-doping behavior due to the oxygen doping effect in air. Figure S5c shows the TLM plots at different V values at a step of 1V. The intercept and the slope of the linear fits of the data reflect the information of contact resistance and intrinsic channel conductivity (Figure S5d). We extracted an intrinsic carrier mobility (μ) of 2800 2 -1 -1 cm V s and a zero-bias square conductivity (σ) of 2.2 mS, suggesting high quality of the CVD graphene used. The extracted contact resistivity of Cr/Au electrode to graphene is also plotted to the right Y axis in Figure S5d. It increases from 0.35 to 0.8 Ω·cm when V changes from -10 to 10V, which is about 10 times higher than that of the Pd/Au contacts (0.02-0.04 Ω·cm). The less perfect contact is likely responsible for the large series resistance of the devices (discussed below). S10 S4: Effect of TFSA doping on CVD graphene 4. Effect of TFSA doping on CVD graphene a b 0.8 TFSA: 0.6 Pristine 0.4 TFSA 0.2 After TFSA doping 0.0 -10 -5 0 5 10 V (V) After TFSA doping Pristine  = 8.8 mS, V = 0 2 -1 -1  = 760 cm V s  = 2.2 mS, V = 0 -6 2 -1 -1  = 2800 cm V s Pristine After TFSA doping -12 -10 -5 0 5 10 0.0 0.2 0.4 0.6 V (V) Bias (V) Figure S6 Effect of TFSA doping on electronic performance of CVD graphene and related photodiodes. a, Diagram of TFSA doping and Fermi level engineering of graphene. b, Variation of contact resistivity by doping. c, Change of channel conductivity and carrier mobility by doping. d, Improvement of photoresponse after doping. Figure S6a show the diagram of engineering the Fermi level of graphene. Since TFSA is a strong electron-drawing molecule, upon spinning coating it on graphene, it is expected to highly dope graphene and downshift the Fermi level via charge transfer. Electronically, the TFSA doping has three effects: 1) It reduces the contact resistivity to 0.2 Ω·cm in most Vg regime (Figure S6b); 2) It increases σ of graphene from 2.2 to 2 -1 -1 8.8 mS at V =0; 3) It degrades from 2800 to 760 cm V s , because the TFSA molecules are randomly distributed charges above graphene, which serves as additional scattering centers. Although the third effect is detrimental to photoresponse, the residual mobility remains high enough to support the photocarrier transport. After TFSA doping, the overall device performance is much improved by the first two favorable effects. A large increase on both short-circuit current (J ) and open-circuit sc voltage (V ) is observed (Figure S6d). oc S11 Square conductivity,  (mS) Current density, J (mA/cm ) Contact resistivity (cm) S5: Effect of HNO doping on mechanically exfoliated graphene 5. Effect of HNO3 doping on3 mechanically exfoliated graphene st nd rd th 1 : Pristine 2 : HNO vapor 40s 3 : 150°C, 10min 4 : + HNO vapor 20s 3 3 b 10 μm 2L 3L + 1L G18-A 2nd nd 2 : 1000 Ω/☐ 4th: 1400 Ω/☐ 4th 1st rd 3 : 1400 Ω/☐ 2nd 3rd 3rd st 1st 1 : 2000 Ω/☐ -6 4th 1st 10 mv/ 6 uA = 2 kΩ 2nd 3rd 10 mv/ 12 uA = 1 kΩ -12 4th -10 0 10 20 30 40 -0.5 0.0 0.5 • conductivity ↑ V (V) Bias (V) • mobility ↓ Figure S7 Effect of HNO doping on electronic performance of mechanically exfoliated graphene and related photodiodes. a, Diagram of different doping levels. b, Transfer curves at different doping levels. c, Variation of photoresponse curves at different doping levels. Figure S7 show sequential experiment results of HNO doping on an individual device at four stages: 1) Pristine; 2) HNO vapor exposure by 40 s; 3) Heated at 150 °C by 10min; 4) Re-exposure of HNO vapor by 40 s. The schematic diagrams are shown in Panel a. Panel b shows the transfer curve at the four conditions, exhibiting quite similar trends with TFSA doping, that is, σ increases and μ decreases upon doping (Stage 1 to 2), reflecting the effect of charge transfer and effective doping. In the stage 3 of heating (150 °C, 10min), σ decreases and μ is unchanged, which means degradation of contact. This is consistent with the S-shape photocurrent curve (green line, panel c). In the stage 4 of re-exposure of HNO vapor, no large improvement in σ but further μ degradation are seen, indicating the saturation in doping. Further exposure to HNO vapor will only increase the defect density in graphene and there is no recovery of the photocurrent curve (blue line, panel c) because HNO can produce carbon vacancies by reaction with graphene. S12 Current of graphene (A) Current density, J (mA/cm ) 6. Refractive indices of candidate antireflection capping layers TiO PMMA MoO 2 3 SiO ZnO Si N 2 3 4 MgF SiC sqrt(n ) 2 si 400 500 600 700 800 Wavelength (nm) Figure S8 Refractive index values for several candidate antireflection capping layers and the ideal values (𝑛 = 𝑛 𝑛 ). 𝑟𝑎𝑖 S13 Refractive index 𝑠𝑖 𝐴𝑅 7. Design of MoO3 antireflection layer S6: Design of MoO antireflection layer a b 120 120 Theoretical (wo. graphene) Theoretical (wi. graphene) 100 100 80 80 60 60 wo. MoO wo. MoO 3 3 40 40 50 nm MoO 50 nm MoO 3 3 80 nm MoO 80 nm MoO 20 20 3 3 110 nm MoO 110 nm MoO 3 3 0 0 400 600 800 1000 400 600 800 1000 Wavelegnth (nm) Wavelegnth (nm) 120 120 Theoretical Experimental 100 100 55 nm MoO AR 80 55 nm MoO AR wo. MoO AR wo. MoO AR 3 40 40 1-R EQE 300 400 500 600 700 800 300 400 500 600 700 800 Wavelegnth (nm) Wavelegnth (nm) Figure S9 Design and application of MoO antireflection layer. a, Calculated absorption (1-R) for different AR thicknesses without placing graphene. b, Corresponding results with placing graphene. No noticeable difference can be seen between a and b. c, Calculated absorption (1-R) curves for zero and 55 nm MoO AR. d, Corresponding experimental data on absorption (1-R) and EQE. The application of antireflection (AR) layers is a common technique to increase the device photoresponse. Theoretical calculation was used for rational design of the thickness of the MoO AR layers. We first identified that the ultrathin layers (such as graphene and TFSA) have negligible effect on the optical reflection. Figure S9 a-b compare the calculated absorption (1-R) curves with and without graphene in the layered devices. As can be seen, the 1-R curves are nearly identical at each MoO thickness. Hence, for simplification we neglected the ultrathin layers of graphene and TFSA in later calculations. In Figure S9b, one can find that a MoO layer with thickness between 50-80 nm can enhance the 1-R values in most visible range. In experiment, we used 55 nm MoO . Figure S9c plots the calculated 1-R curves for devices with bare and 55 nm MoO S14 1-R (%) 1-R (%) 1-R and EQE (%) 1-R (%) AR layers. Evidently, upon depositing the MoO3 AR layer, the 1-R values are enhanced in the whole visible regime. In particular, the 1-R can be enhanced from 60% to 100% at 450 nm due to the destructive interference in reflection. We also determined the real 1-R curve with reflection spectroscope from 400 to 800 nm (blue and red lines, Figure S9d) and calculated the external quantum efficiency (EQE, blue and red circles, Figure S9d) from 300 to 700 nm. Both values (1-R and EQE) are quite close at each wavelength, implying a nearly unity internal quantum efficiency (IQE = EQE/(1-R)) and a high interface quality of our devices fabricated with the nano-subsidence technique. Overall, the experimental curves shown in panel d agree reasonably with the calculation shown in panel c. S15 S8: Effect of graphene work function on V 8. Effect of barrier height (ΦB) on Voc oc a b Graphene/Si Graphene/Si TFSA doped TFSA + MoO MoO TFSA TFSA Graphene/Si 2 Graphene/Si Exp. 0 Fit 0.1 0.2 0.3 0.1 0.2 0.3 Bias (V) Bias (V) 0.84 Graphene/Si OC TFSA + MoO + TFSA 0.81 0.3 0.78 TFSA MoO 0.75 TFSA -6 0.45 0.50 0.55 V (V) Graphene/Si OC -12 0.0 -18 0.1 0.2 0.3 0.0 0.1 0.2 0.3 0.4 0.5 Bias (V) Bias (V) Figure S10 Dependence of open-circuit voltage Voc on barrier height ΦB. a-c, Fits of barrier height by thermionic-emission equation at varied doping levels. Insets: Diagram of doping schemes. d, Photoresponse curves at different doping levels where V changes accordingly. Inset: Plot of Φ and V at different oc B oc doping levels. We also investigated the relation of barrier height (Φ ) and V . Φ was tuned by B oc B changing the work function of graphene via doping levels. Three doping levels were achieved by consequently applying TFSA, MoO3, and a second TFSA; the doping schemes were shown in the insets of Figure S10 a-c, respectively. The values of Φ were estimated by fitting the I-V curves with the thermionic-emission equation 𝛷 𝑉 ∗∗ 2 𝐽 = A 𝑇 exp ( − ) [exp ( − ) − 1] dark -2 -2 where 𝐽 is the dark current and A**=252.4 A·cm ·K is the Richardson constant dark along the <100> direction of silicon. The fits are represented by the red lines in Figure S10 a-c, which agree well with the experimental data. The extracted Φ are 0.786, 0.770, and 0.825 eV for the above doping levels, corresponding to V of 0.495, 0.475, oc and 0.548 V, respectively (Figure S10d). It is found that V exhibit a linear oc dependence on Φ , as shown in the inset of Figure S10d. S16 Current (A/m ) Current (A/m ) 2 2 Photocurrent (mA/cm ) Current (A/m ) Barrier height (eV) 𝑛𝛽 9. Fit of series resistance a b 0.2 Rectification ratio = 10 -1 -2 -3 -4 0.1 -5 R = 1.9 k,n = 2.23 -6 -7 -1.0 -0.5 0.0 0.5 1.0 0 30 60 90 V (V) Current, I (A) Figure S11 Fit of series resistance with the transformed thermionic-emission equation. a, Semi-logarithmic plot of the I-V curves of a TFSA doped graphene/silicon junction under dark condition, where a high rectification ratio of 10 is observed. b, Fitting the I-V curve to extract the junction parameters: series resistance R and ideality factor n. Inset: Optical image of the corresponding device before SiO etching. The series resistance (R ) of the TFSA doped device was fitted with the 3,4 transformed thermionic-emission equation d𝑉 𝑛 = 𝑅 𝐼 + ( ) d ln𝐼 𝛽 where n is the ideality factor and 𝛽 = 𝑒 / is the inverse thermal voltage. Figure S11 show the experimental data and related fit. The values of R and n are estimated to be 1.9 kΩ and 2.23, respectively. Given the dimension of the device (100×100 μm , inset of Figure S11b), the normalized R is 0.19 Ω/cm , consistent with previous reports. S17 Current, I (A) dV/d(lnI) (V) 𝑘𝑇 Filling Factor Filling Factor Filling Factor Filling Factor 10. Performance as photovoltaic devices S9: Performance as photovoltaic devices 8.3% 36% 520 nm a 520 nm b Graphene/TFSA/MoO Graphene/TFSA 3 Si Si TFSA → doping graphene 55 nm MoO → antireflection layer 0 1.0 0 1.0 ID: CVDG14_F ID: CVDG14_F (0.0106 mm , TFSA) (0.0106 mm , MoO AR) 2 0.8 0.8 520 nm, 44.8 mW/cm -5 520 nm, 44.8 mW/cm V = 0.545 V OC V = 0.578 V -5 OC 0.6 0.6 J = 11.3 mA/cm SC J = 15.6 mA/cm SC FF = 0.734 -10 FF = 0.769  = 10.1% 0.4  = 15.6% 0.4 -10 -15 0.2 0.2 -15 0.0 -20 0.0 0.0 0.2 0.4 0.6 0.0 0.2 0.4 0.6 Bias (V) Bias (V) AM1.5 AM1.5 Graphene/TFSA/MoO Graphene/TFSA 3 Si Si TFSA → doping graphene 55 nm MoO → antireflection layer 0 1.0 0 1.0 ID: CVDG14_F ID: CVDG14_F 2 2 (0.0106 mm , TFSA) (0.0106 mm , MoO AR) 2 0.8 0.8 AM1.5, 100 mW/cm AM1.5, 100 mW/cm V = 0.579 V OC V = 0.597 V -10 -10 OC 0.6 0.6 J = 22.5 mA/cm J = 25.9 mA/cm SC SC FF = 0.696 FF = 0.704  = 9.07%  = 10.9% 0.4 0.4 -20 -20 0.2 0.2 -30 0.0 -30 0.0 0.0 0.2 0.4 0.6 0.0 0.2 0.4 0.6 Bias (V) Bias (V) Figure S12 Comparison of photovoltaic parameters at different device configuration and illumination conditions. a, No AR layer under monochromatic illumination. b, Optimized AR layer under monochromatic illumination. c, No AR layer under AM1.5 illumination. d, Optimized AR layer under AM1.5 illumination. Figure S12 show the complete device performance as photovoltaic cells, characterized under different device configuration (with or without MoO AR layer) and illumination conditions (monochromatic illumination/ reduced power and standard AM1.5 condition). The detailed device parameters are summarized below. Device MoO3 Filling Photoconversion Illumination Voc Jsc No. (nm) factor, FF efficiency, η 1 0 520 nm, 0.545 11.3 0.734 10.1% 2 55 44.8 mW/cm 0.578 15.6 0.769 15.6% 3 0 0.579 22.5 0.696 9.07% Standard AM1.5 4 55 0.597 25.9 0.704 10.9% S18 2 2 Photourrent (mA/cm ) Photourrent (mA/cm ) 2 2 Photourrent (mA/cm ) Photourrent (mA/cm ) 11. Output power and linearity of monochromatic light source Forward Backward 0 0 300 400 500 600 700 0 20 40 60 80 100 Wavelength (nm) Setting power percentage (%) Figure S13 Output power and linearity of monochromatic light source employed in experiment. a, Output power as a function of light wavelength where the power peaks at 470 nm. b, Test of power linearity of the control system. Reference (1) Xia, F.; Perebeinos, V.; Lin, Y.-M.; Wu, Y.; Avouris, P., The Origins and Limits of Metal-Graphene Junction Resistance. Nat. Nanotechnol. 2011, 6, 179–184. (2) Sze, S. M.; Ng, K. K., Physics of Semiconductor Devices. 3rd edn., John Wiley & Sons, New Jersey, 2007. (3) Werner, J. H., Schottky Barrier and pn-Junction I/V Plots – Small Signal Evaluation. Appl. Phys. A 1988, 47, 291–300. (4) Shi, E.; Li, H.; Yang, L.; Zhang, L.; Li, Z.; Li, P.; Shang, Y.; Wu, S.; Li, X.; Wei, J.; Wang, K.; Zhu, H.; Wu, D.; Fang, Y.; Cao, A., Colloidal Antireflection Coating Improves Graphene-Silicon Solar Cells. Nano Lett. 2013, 13, 1776–1781. S19 Power (W) Real power (W) http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png Physics arXiv (Cornell University)

Nano-Subsidence Assisted Precise Integration of Patterned Two-Dimensional Materials for High-Performance Photodetector Arrays

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10.1021/acsnano.9b00889
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Published at ACS Nano 13, 2654 (2019), doi: 10.1021/acsnano.9b00889 Nano-Subsidence Assisted Precise Integration of Patterned Two- Dimensional Materials for High-Performance Photodetector Arrays 1,2* 1 1 1 1 Song-Lin Li, Lei Zhang, Xiaolan Zhong, Marco Gobbi, Simone Bertolazzi, Wei 3 3 3 1§ * 1* Guo, Bin Wu, Yunqi Liu, Emanuele Orgiu, Paolo Samorì University of Strasbourg, CNRS, ISIS UMR 7006, 8 allé e Gaspard Monge, F-67000 Strasbourg, France National Laboratory of Solid State Microstructures, School of Electronic Science and Engineering and Collaborative Innovation Center of Advanced Microstructures, Nanjing University, Nanjing 210023, China Beijing National Laboratory for Molecular Sciences, Institute of Chemistry, Chinese Academy of Science, Beijing 10086, China Present address: Institut national de la recherche scientifique (INRS), EMT Center, 1650 Blvd. Lionel-Boulet, J3X 1S2 Varennes, Canada Corresponding Authors E-mail: sli@nju.edu.cn (S.L.L), emanuele.orgiu@emt.inrs.ca (E.O.), samori@unistra.fr (P.S.) 1 Published at ACS Nano 13, 2654 (2019), doi: 10.1021/acsnano.9b00889 ABSTRACT The spatially precise integration of arrays of micro-patterned two-dimensional (2D) crystals onto three-dimensionally structured Si/SiO substrates represents an attractive strategy towards the low-cost system-on-chip integration of extended functions in silicon microelectronics. However, the reliable integration of the arrays of 2D materials on non-flat surfaces has thus far proved extremely challenging due to their poor adhesion to underlying substrates as ruled by weak van der Waals interactions. Here we report on a novel fabrication method based on nano-subsidence which enables the precise and reliable integration of the micro-patterned 2D materials/silicon photodiode arrays exhibiting high uniformity. Our devices display peak sensitivity as high as 0.35 A/W and external quantum efficiency (EQE) of ~90%, outperforming most commercial photodiodes. The nano-subsidence technique opens a viable path to on-chip integrate 2D crystals onto silicon for beyond-silicon microelectronics. 2 Published at ACS Nano 13, 2654 (2019), doi: 10.1021/acsnano.9b00889 MAIN TEXT With Moore’s law reaching its limit , the semiconductor industry is urgently searching for innovative strategies to go beyond standard microelectronics. One of the most recent and intriguing strategies in modern electronics, referred to as system-on- 2-4 chip (SoC) for more-than-Moore electronics , aims to integrate various active modules in individual chips wherein different functional materials are combined with standard silicon technology. This hybrid approach enables the introduction of extended functionalities such as data storage, sensing, communication and self- powering to conventional logic modules, therefore expanding the current capabilities 5-9 of logic microelectronics. In this context, two-dimensional (2D) atomic crystals , which include a vast library of materials with each one featuring distinctive physical and electronic properties, have emerged as outstanding candidates for integration into silicon to create hybrid devices with unique capabilities . For the purpose of SoC application, different materials are required to be hetero- integrated onto silicon through direct contact or interconnection . Previous reports revealed that 2D crystals could be directly transferred onto three-dimensionally 11-13 14-16 17 structured silicon for energy harvesting , photonics , and electronics , providing evidence for their potential as on-chip functional modules. However, in such experiments the cumbersome fabrication process following the 2D crystal transfer needs to be minimized, since the atomically thin 2D crystals are prone to shear from or even to come off the substrate during microfabrication processing such as photoresist deposition and pattern development. These fabrication issues severely hamper the applicability of patterning large 2D sheets into micrometric functional arrays as active SoC components. For these reasons, to date such hybrid devices are mostly restricted to large 2D sheets forming individual active units; the precise and stable integration of arrays of micro-patterned 2D crystals for advanced electronics has remained elusive. Here, we have devised a nano-subsidence integration method which enables spatially precise and high-yield integration of arrays of micro-patterned 2D crystals onto a three-dimensional substrate such as a patterned Si/SiO surface. Such method enables the fabrication of high performance arrays of photodetectors. As a proof of concept, 2 × 2 type four-quadrant 2D crystal/silicon diodes used as photodetectors are demonstrated. By engineering the optical antireflection and graphene work function, our photodetectors exhibit remarkably high peak sensitivity up to 0.35 A/W and EQE of ~90% at 480 nm, as well as high spatial uniformity. 3 Published at ACS Nano 13, 2654 (2019), doi: 10.1021/acsnano.9b00889 Depending on the optical wavelength range, the overall system performances are comparable to or higher than those of commercial silicon diode-based photodetectors. The conventional method for integrating 2D crystals into silicon-based technology consists in their direct transfer onto three-dimensionally predefined Si/SiO 11-15,17,18 substrates , as portrayed in Fig. 1a. In this approach, the SiO capping above silicon is used as both sacrificing and insulating layers. Selected SiO sacrificing areas are pre-etched to open a window, which allows direct contact between the 2D crystals and underlying silicon, serving as active functional region; the rest SiO areas around the window work as insulating layers for external wiring, resulting in stepwise substrate surfaces . When 2D crystals are transferred over patterned surfaces, they have to physically adapt to the patterns in relief. Since the 2D crystals cannot uniformly land on the top part(s) of the relief(s) and on the surface during a mechanical transfer process, the poor adhesion between 2D crystals and the substrate 20,21 leads to the emergence of physical corrugations and bubbles . In turn, such weak substrate adhesion causes the sliding off or even removal of 2D crystals in the subsequent lithography processing necessary for patterning the 2D crystals or defining microelectrodes. Moreover, it is extremely challenging to precisely align all the micrometric 2D crystals at the desired positions on pre-patterned substrates, as it relies on manual alignment and operation under optical microscope, where location uncertainty is within several micrometers . Thus, by employing a conventional method, it is almost impossible to integrate arrays of micrometric 2D crystals onto three-dimensional substrates with spatial precision and at high yield. To address the above-mentioned challenges, we have conceived the nano- subsidence integration method that allows a high-yield hetero-integration (Fig. 1b). The method relies on the metallization before the 2D crystal patterning and SiO etching, in order to use the solid electrodes as anchoring bars to prevent the 2D crystals from shearing during the following processing. The alignment among 2D crystals, electrodes, and step edges can then be accurately defined through photolithography, ensuring high spatial precision in the hetero-integration. The third consideration is to etch the SiO sacrificing areas in the last fabrication step and the arrays of micro-patterned 2D crystals can gently subside, taking advantage of the flexibility of the ultrathin 2D crystals, and adapt to the stepwise substrates with negligible strain and improved adhesion. As an additional benefit, the formation of hetero-junctions between 2D crystals and silicon takes place in the last step, avoiding 4 Published at ACS Nano 13, 2654 (2019), doi: 10.1021/acsnano.9b00889 exposure of the fresh silicon surface to air thereby avoiding any environmental contamination. Figure 1c sketches the individual processing steps of the novel integration technique while showing corresponding optical microscopy images. First, the large- area CVD graphene is transferred onto a flat SiO /Si substrate. Graphene adheres well to the substrate thanks to the large contact area and the superior flatness of the pristine SiO surface. Metal electrodes with a given pattern are then deposited onto graphene through a standard photolithographic process followed by thermal evaporation of the metal and a lift-off step. Afterwards, graphene is patterned through photolithography and oxygen plasma etching. Finally, the SiO layer in the device active region is wet etched via a photoresist mask, so that the graphene layers gently fall down and make contact to the exposed silicon. After thoroughly rinsing in deionized water, the samples are dried out in vacuum to desorb the encapsulated water between graphene and silicon. By means of the capillary action formed during the vacuum evaporation of the encapsulated water, the graphene is in conformal contact with silicon. We found that the crystal/silicon adhesion is readily wetting-enhanced and is much superior to that formed in the simple dry transfer. As a proof of concept, we apply this method to demonstrate a four-quadrant graphene/silicon photodiode detector, a typical beam position sensing module widely used as collimators and many other adjustment sensors in fiber communication and 22-24 space guidance . The yield of the subsidence integration of graphene to silicon was considerably high: 34 out of 36 quadrants were attained without obvious breaking or folding of graphene, thereby attesting a yield as high as 94 % (supplementary Fig. S2). We note that our approach is extremely versatile and the prototypical 2×2 array fabricated here (Fig. 1c) can be easily upgraded into more complicated arrays/devices. Alongside the use of a novel integration method, we have paid particular attention towards the engineering energy levels of graphene which is known to be essential for 11,13 attaining high photosensing performance . Figure 2a depicts the energy level alignment and working principle of the graphene/silicon photodiodes. The electron- hole pairs are first generated by light irradiation on silicon; then holes drift into graphene assisted by the built-in electric field at the graphene/silicon interface. Hence, the built-in electric field is the driving force for carrier separation and a high built-in electric field would be favorable for this process. In addition, a large interfacial 5 Published at ACS Nano 13, 2654 (2019), doi: 10.1021/acsnano.9b00889 barrier helps to block the drift of electrons to graphene, reducing the carrier recombination in graphene. 25 2 -1 -1 A high-quality CVD graphene with an intrinsic carrier mobility of 2800 cm V s (supplementary Fig. S3d) was used in this work. To increase the interfacial barrier, we implement p-type doping of graphene via spin-coating a thin layer of bis(trifluoromethanesulfonyl)amide (TFSA, [CF SO ] NH, inset of Fig. 2b), a strong 3 2 2 13,26 electron-withdrawing molecule . In contrast to the weak doping effect by ambient oxygen and water molecules with a shift of charge neutrality point of 17 V (supplementary Fig. S3a), the TFSA doping determines a larger shift of ~270 V (supplementary Fig. S4c). Such a large shift corresponds to a rather high surface 13 -2 doping concentration of 6.5×10 cm and a work function increase of 0.75 eV in graphene, as estimated through the equation 𝜀 = ℏ ∙ 𝑣 ∙ , where 𝜀 , 𝑣 , 𝑛 , and ℏ F F F F denote Fermi energy, Fermi velocity, carrier concentration, and reduced Planck constant, respectively. The strong doping caused an effective interfacial barrier of 0.79 eV (supplementary Fig. S8d). Accordingly, improved photovoltaic behavior was achieved, as confirmed in Fig. 2b by the current-voltage (I-V) characteristics of the pristine and doped devices. TFSA-doped devices exhibited highly enhanced open- circuit voltage (V ), short-circuit current (I ), and fill factor (FF), indicating the OC SC critical role of the interfacial barrier on the photovoltaic performance. In Fig. 2c, we analyzed the I-V behavior of the doped device under dark condition, which reveals a good ideality factor of 2.02 and a high rectification ratio of 10 in the bias range of ±1 V, suggesting an excellent photodiode junction quality. The excellent junction quality is also corroborated by the photovoltaic tests. Before antireflection coating, the doped device shows high photovoltaic efficiencies of 10.1% and 9.1% under 520 nm/43.5 -2 mW· cm and AM1.5 conditions, respectively (supplementary Fig. S10 a and c), 11-13 consistent with the literature results. The series resistance (R ) value was 2 2 estimated to be 0.26 Ω/cm for the 100×100 μm device, which outperforms that of previous reports with device fabricated by direct transfer . We have also measured the response speed of the photodiode under a monochromatic light source. Figure 2d shows a diagram of the piezoelectrically controlled monochromator used in our experiments. The angle of the incoming light from the Xenon lamp is fixed while the angle of reflection beam and the resulting wavelength of the outcoming beam through the slit would change upon piezoelectrical 𝜋𝑛 Published at ACS Nano 13, 2654 (2019), doi: 10.1021/acsnano.9b00889 rotation of the optical grating. Since the light power varies with wavelength (the characteristic spectrum of the system is given in supplementary Fig. S11), a modulated photoelectric response would be observed with changing the optical wavelength. Figure 2e displays the modulated photocurrent modes when the incident light wavelength changes from 500 nm to 300, 350, 400 and 450 nm, respectively. At shorter time scales (Fig. 2f) both the rise and decay time are within 500 μs, which represents the fastest signal that can be detected through our experimental setup limited by the millisecond-scale piezoelectric response rate of the grating driver. Hence, the response speed of our devices, of at least 500 μs, certainly represents an underestimate. Generally, the response time would be longer if the density of interfacial states and charge trapping centers were sizeable. The fast response featured by the devices made with our nano-subsidence method suggests that the graphene/silicon interface of the photodiodes is of high quality. In order to further optimize the performances of our photodiodes, we have employed a surface antireflection capping. This is commonly employed to increase the optical absorption of photodiodes by depositing single or multiple optically 11,28-31 transparent antireflection dielectrics . According to the principle of optical destructive coherence, the reflection rate for a certain light will be minimized when a single antireflective capping layer satisfies the double conditions that 𝑛 = √𝑛 𝑛 𝑟𝑎𝑖 and 𝑑 = 𝜆 /4𝑛 , where 𝑛 , 𝑛 , and 𝑛 are the refractive indices of the 𝑟𝑎𝑖 antireflective capping layer, air and silicon, respectively, and 𝑑 and 𝜆 are the thickness of the capping layer and the incident light wavelength. Given the atomic thickness of the 2D layers and the low formation energies of lattice defects that make 32-34 them prone to damages generated by external high-energy atoms, capping layers grown via aggressive deposition methods (e.g. sputtering) should be avoided. 30,31 Towards this end, we have used thermally evaporated MoO as the capping layer, and the damage to 2D layers are expected to be minimized. The values of 𝑛 are 𝑂𝑀𝑜 3 close to those of 𝑛 𝑛 in most range of visible light (supplementary Fig. S6), 𝑟𝑎𝑖 suggesting that it is a suitable antireflection material. By theoretical calculations, we also confirmed that the effect of graphene on optical absorption is negligible due to its atomic thickness (supplementary Fig. S7). Figure 3a sketches the device cross section of pristine versus capped devices and their related optical images. Micro-area reflection measurement revealed that the 𝑠𝑖 𝐴𝑅 𝑠𝑖 𝐴𝑅 𝐴𝑅 𝐴𝑅 𝑠𝑖 𝐴𝑅 Published at ACS Nano 13, 2654 (2019), doi: 10.1021/acsnano.9b00889 reflectivity is remarkably reduced from 36% to 8% at  = 520 nm upon the use of a capping layer of 55-nm MoO . The reduction of the optical reflection is also corroborated by the difference in brightness of the optical images of the pristine and capped silicon/graphene stacks, where a lower brightness is observed in the latter (around orange dot in the lower panels of Fig. 3a). As a result, the photoresponse of the devices is enhanced. Under 43.5 mW/cm illumination at 520 nm, the photocurrent increases from 11.6 to 16.7 mA/cm (Fig. 3b). The effect of the MoO3 antireflective capping is further analyzed by correlating micro-area reflection spectra to the external 𝐽 ħ𝐶 𝑝 ℎ quantum efficiency (EQE) of our devices. Here EQE is estimated by EQE = 𝑒𝑃𝜆 where 𝐽 is the photocurrent density, C is the speed of light within vacuum, 𝑒 is the 𝑝 ℎ elementary charge, P is the light power. The EQE data was extracted from the photocurrent spectrum recorded between 320 to 690 nm. The open blue and red circles in Fig. 3c compare the EQE before and after deposition of a 55-nm-MoO capping layer. As expected, the capping enhances (or reduces) the EQE around  = 480 (or  = 320 nm), in agreement with the interference conditions at the corresponding wavelengths (supplementary Fig. S7c). In Fig. 3c, we also compare the EQE with device absorption rate (1-R, with R the reflectivity) as measured by micro- area reflection. The EQE lines follow closely with the absorption rates, suggesting a near-unity internal quantum efficiency (IQE) since IQE=EQE/(1-R). In the experiments, the peak IQE reaches 90% at 480 nm, approaching the ideal unitary IQE of the photodiodes . The ~10% reduction to the ideal values (supplementary Fig. S7, c and d) stems likely from local variations of refractive index in the MoO capping layer caused by the presence of pinholes or oxygen loss. The extremely high IEQ achieved here corroborates again the high integration quality of the arrays via our nano-subsidence method. The photocurrent properties of the capped devices were extensively characterized by varying the optical wavelength and power. Figure 3d plots the photoelectric sensitivity versus the two parameters of light wavelength and power. Despite of strong dependence on light wavelength, the sensitivity is basically power independent within the measurement range of optical power (from 10% to 100%) since the devices show negligible saturation in photoresponse below 100% power (Fig. 3e). To evaluate the potential of the nano-subsided photodiodes as a system-on-chip module, we also compare the EQE of our devices in Fig. 3f and Table 1 with currently commercial 8 Published at ACS Nano 13, 2654 (2019), doi: 10.1021/acsnano.9b00889 photodiodes based on silicon pn junctions (ThorLabs FDS010 and FDS10×10, Hamamatsu S1336BQ). Remarkably, our devices are superior to their commercial counterparts in the visible region from 400 to 700 nm, therefore representing a prototypical high-performance system-on-chip module for the beyond-silicon circuitry. To assess the photoresponse uniformity of individual array units, we mounted our samples onto a test printed circuit board (PCB) (Fig. 4a). In order to have a reliable (wire) bonding to device electrodes, no MoO capping layer is deposited in this test. Figures 4b and 4c show enlarged images on local arrays at different magnification ratios where multiple quadrant photodiodes were prepared. During testing, each unit was exposed to a 532-nm focused laser beam with a power of about 10 W/cm . Figures 4d-4f show the corresponding photoelectric curves. Almost identical I-V curves were recorded for the four units, with I =0.56±0.08 μA. A slight degradation SC of the fill factor was observed in all the four I-V curves, which is likely due to the effect of ambient moisture on the hygroscopic dopant TFSA during the measurements. Finally, we have verified the generalization of the nano-subsidence assisted integration method by replacing graphene with another renowned 2D crystal, i.e. molybdenum disulfide (MoS ). Figure 5a shows the optical images of a MoS /silicon 2 2 junction before and after SiO etching. A mechanically exfoliated 5-layer-thick MoS 2 2 was used in this device. Since MoS is normally slightly n-doped, the MoS /silicon 2 2 ++ stack can be regarded as an n/n homo-junction with relatively small barrier heights . Figure 5b shows a corresponding band diagram, where Φ and Φ are the barriers C V for blocking the reverse motions of electrons and holes at the conduction and valence bands, respectively. Owing to smaller Φ and Φ as compared to the case of doped C V graphene/silicon (Fig. 2a), a large number of carriers can drift and recombine, resulting in lower V and J (Fig. 5c) and a reduced fill factor (Fig. 5d). However, OC SC in spite of the degraded photoelectric properties with respect to graphene/silicon junctions, the MoS /silicon junction still exhibited a photoelectric behavior similar to that of small-barrier diodes in which backward current is enhanced and reasonably high other photoelectric parameters. In particular, a large rectification ratio of 10 within ±1 V (Fig. 5c), notable photoelectric behavior (Figs. 5c and 5d), reasonably high peak EQE of ~25% (Fig. 5g), and fast photoresponse of 1 ms (Fig. 5h) are measured. 9 Published at ACS Nano 13, 2654 (2019), doi: 10.1021/acsnano.9b00889 In conclusion, we have developed a novel method enabling the integration of atomically thin 2D crystals for the system-on-chip electronics, through the precise location of ultrathin crystals and on-chip integration of arrays of micro-patterned 2D crystals with a minimized residual strain of the 2D crystals on non-flat substrates. Noteworthy, this integration method combines several advantages. First, the substrate surface was kept flat in all photolithography steps (i.e., metallization, patterning 2D crystals, and defining mask for SiO etching), which facilitates the microfabrication processing such as resist coating. Second, high-yield integration of 2D crystals into the stepwise substrate was realized via controlled gentle subsidence assisted by capillary forces during vacuum dry, which also ensures a precise positioning and alignment of the micrometric 2D crystals onto the target electrodes. Third, the exposure of bare silicon surface to air is minimized, resulting in a high quality of the 2D material/Si interface which, as a result, improves the junction performances. Taking graphene and MoS as model systems, we demonstrated the general applicability of such unique integration method to integrate all kinds of 2D crystals onto silicon as photodiodes. The photodetector performances surpass those of commercial photodiodes after appropriate device optimization. Not limited to the photoelectric function and materials demonstrated above, the concept of subsidence integration via an underlying sacrificial layer could also be extended to wider applications, such as 3D interconnection, optical waveguides, and microfluidic channels, and hence it holds great potential for realizing more versatile modules for the beyond-silicon more-than-Moore microelectronics. Acknowledgments We acknowledge funding from the European Commission through the Graphene Flagship (GA-696656), the FET project UPGRADE (GA-309056) and Marie-Curie IEF MULTI2DSWITCH (GA-700802), the M-ERA.NET project MODIGLIANI, the Agence Nationale de la Recherche through the Labex projects CSC (ANR-10-LABX- 0026 CSC) and Nanostructures in Interaction with their Environment (ANR-11- LABX-0058 NIE) within the Investissement d’Avenir program (ANR-10-120 IDEX- 0002-02), and the International Center for Frontier Research in Chemistry (icFRC). This project is also partially supported by the National Key R&D Program of China (2017YFA0206304) and the National Natural Science Foundation of China (61674080). 10 Published at ACS Nano 13, 2654 (2019), doi: 10.1021/acsnano.9b00889 Author contributions S.L.L., E.O. and P.S. conceived the experiment and designed the study. S.L.L. performed the experiments and developed the fabrication method. W.G., B.W, and Y.L. synthesized and provided the CVD graphene sample. S.L.L., E.O. and P.S. co- wrote the paper. All authors discussed the results and contributed to the interpretation of data, as well as contributing to editing the manuscript. Additional information Supplementary information is available in the online version of the paper. Reprints and permissions information is available online at www.nature.com/reprints. Correspondence and requests for materials should be addressed to S.L.L., E.O. and P.S. Competing financial interests The authors declare no competing financial interests. Table 1 Comparison of EQE performance of nano-subsidence fabricated graphene/silicon photodiode with typical commercial silicon photodiodes at different wavelength values. The values in parentheses show the EQE difference of the commercial devices as compared to our graphene/silicon device. EQE EQE EQE EQE EQE Photodiode @ 350 nm @ 450 nm @ 500 nm @ 550 nm @ 650 nm This work 27.2% 84.2% 90.3% 89.0% 86.2% ThorLabs 58.9% 68.6% 73.6% 76.5% 79.0% FDS10×10 (+117%) (-19%) (-18%) (-14%) (-18%) (UV enhanced) Hamamatsu 56.1% 60.8% 63.7% 65.7% 67.5% S1336BQ (+106%) (-28%) (-29%) (-26%) (-22%) (UV enhanced) ThorLabs 19.0% 40.8% 54.2% 64.5% 76.8% FDS010 (-30%) (-52%) (-40%) (-28%) (-11%) 11 Published at ACS Nano 13, 2654 (2019), doi: 10.1021/acsnano.9b00889 Methods Transfer of CVD graphene on flat SiO /Si substrates. Large-area high-quality monolayer graphene was grown on 25 μm thick copper foils by CVD . A 20 mg/mL PMMA/chlorobenzene solution was spin-coated on the graphene/copper foils at 3000 rpm for 30 s, which was then heated dry on a hot plate at 180 ° C for 1 minute. A PDMS scaffold with a hole of ~10 mm in diameter was gently pressed down onto the PMMA/graphene/copper stacks, with the PDMS scaffold attaching to the stacks. Afterward, the whole stack was placed floating on an ammonium persulfate (0.1 M) solution with the copper face downwards to etch the copper foil. After removing the copper foils, the PDMS/PMMA/graphene stack was rinsed in distilled water for several times and was finally scooped out by a flat SiO /Si substrate. The silicon wafers (from IPMS Fraunhofer Institute, Dresden) were capped with a 90-nm-thick thermally grown SiO dielectric layer and were n-doped to a high level of ∼3 × 10 −3 cm . Device fabrication. Optical lithography was performed through a direct laser writing system (LW405B, Microtech Inc.). A thin positive photoresist AZ1505 was used as a mask for graphene patterning and metallization. The exposure resolution is about 1 μm. AZ 726 metal- ion free developer and dimethyl sulfoxide were used for resist development and lift- off, respectively. To increase the adhesion ability of resist and development, the surface of silicon wafers was modified by thermally evaporated hexamethyldisilazane molecules before applying the resist. The SiO dielectric layers were etched by standard buffered HF etchant (NH F : HF = 6 : 1). The electrodes were realized by thermal evaporation of 1 nm of chromium and 50 nm of gold. The use of chromium adhesion layer is necessary in order to prevent the unwanted lateral etching the SiO underneath electrodes (See also supplementary Fig. S1). Characterization and measurements. All optical images of graphene and devices were taken with an Olympus BX53M microscope. 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V., Two-Dimensional MoS under Ion Irradiation: From Controlled Defect Production to Electronic Structure Engineering. 2D Mater. 2017, 4, 025078. 16 Figure TOC Light Bias For Table of Contents Only Figure 1 Light a b 2D crystal Bias 30/2 nm Electrode Electrode direct Electrode Etching X nm 2D crystal 2D crystal transfer G/Si junction SiO + 230 nm Insulating SiO 2 A SiO 2 + + - - - Si 650 mm Si Heavily doped Si c Nano-subsidence integration Metallization Graphene patterning SiO etching SiO Q2 Q1 CVD graphene Q3 Q4 100μm 20μm 20μm 20μm Figure 1 Schematic diagrams of hybrid integration by conventional direct transfer and our nano-subsidence techniques. a, Cross-sectional diagram for the conventional direct transfer integration, which features several risks of tearing out and sliding off when the sizes of 2D crystals are small, due to the weak stickability of 2D crystals and the presence of stepwise substrate structure. b, The concept of the improved hybrid integration by nano-subsidence in which the 2D crystals are fixed by using the metallic electrodes as anchoring bars and selectively etching out the sacrificial SiO layer in the last. The hybrid integration is completed after the gentle subsidence of 2D crystals. c, The processing flow and corresponding images for each critical integration step for the subsidence integration. Its processing sequence is renewed to transfer- metallization-patterning-etching to ensure the precise location of 2D crystals. Figure 2 a b c -8 520 nm Ideality factor 44.8 mW/cm =2.02 0.01 Light -9 n-doped Si exp. Graphene Pristine fit 10 520 nm -10 - - 7 5 -2 10 -6 10 + -11 E + Dark -6 TFSA doped -1 0 1 -12 Bias (V) -12 0.0 0.2 0.4 0.6 0.0 0.2 0.4 0.6 Bias (V) Bias (V) d e f 500 nm white light 500 ms 500 ms rotate 500 nm 450 nm optical slit grating 400 nm 4 350 nm 350 nm photodiode 300 nm 5 6 23 24 0 20 40 60 Time (ms) Time (ms) Figure 2 Photoelectric properties of hybrid graphene/silicon diodes prepared by the nano- subsidence integration. a, Diagram of the energy level alignment and operation principle of the graphene/silicon photodiodes. b, Comparative photoelectric behavior of the photodiodes before and after engineering band alignment via TFSA doping. Inset: The molecular structure of TFSA and the change of Fermi level of graphene before and after TFSA doping. c, Fitting of I-V curve under dark condition to extract the ideality factor of the diodes. Inset: Semi-logarithmic plot of the I-V curves under both dark and light conditions. High rectification and zero-bias signal-noise ratios 5 7 of 10 and 10 are observed. d, Principle of wavelength scan for characterizing photoresponse time, where the piezoelectric response time is below the order of ms that defines the lower limit of our samples. e, Modulation of photocurrent by varying the excitation wavelength. f, Enlarged figure to analyze the rise and decay times of our photodiodes which are estimated to be better than 500 μs. J (mA/cm ) Photocurrent (0.1 mA) I (A) Photocurrent (0.1 mA) J (mA/cm ) Figure 3 a b c 8% 100 36% 520 nm AR layer 2 No AR layer 43.5 mW/cm MoO AR 55nm MoO Graphene/TFSA Graphene/TFSA Si Si wo. MoO AR -6 wo. MoO AR -12 1-R EQE MoO AR Si/G Si/G/MoO -18 300 400 500 600 700 800 0.0 0.2 0.4 0.6 SiO SiO /MoO 2 3 Bias (V) Wavelegnth (nm) d e f 0.5 Sensitivity (A/W) This work 650 nm Si/G/MoO 0.4 0.48 550 nm 0.36 0.3 450 nm 0.24 0.2 0.12 Commercial Si diode 0.1 350 nm ThorLabs_FDS10x10 0.00 Hamamatsu_S1336BQ ThorLabs_FDS010 0.0 0 20 40 60 80 100 0 20 40 60 80 100 300 400 500 600 700 Light power (%) Light power (%) Wavelength (nm) Figure 3 Photoelectric properties of graphene/silicon diodes after capping antireflective MoO . a, Cross-sectional diagrams and optical images of the pristine and MoO capped devices. 3 3 b, Comparative I-V behavior of the photodiodes before (blue) and after (red) capping 55 nm MoO antireflective layers. The photocurrent increases from 12 to 17 mA/cm . c, Comparison of absorption rate (1-R, lines) and external quantum efficiency (EQE, open dots) before (blue) and after (red) MoO capping. d, Contour plot of photoelectric sensitivity versus wavelength and light power. e, Sensitivity as a function of light power at different wavelength values from 350 to 650 nm. The devices show negligible saturation in photoresponse within experimental power range of ~50 mW/cm . f, Comparison of EQE with three typical commercial silicon photodiodes. Our devices (red dots) rivals the counterparts in the visible regime from 400 to 700 nm after the MoO antireflective capping. Wavelength (nm) Sensitivity (A/W) Current (mA/cm ) 1-R and EQE (%) EQE (%) Figure 4 a b c d 0.0 e 0.0 Quadrant 2 Quadrant 1 -0.2 -0.2 -0.4 -0.4 -0.6 -0.6 -0.6 -0.3 0.0 0.3 0.6 -0.6 -0.3 0.0 0.3 0.6 Vd,V (dataX) Vd,V (dataX) 0.0 0.0 f g Quadrant 3 Quadrant 4 -0.2 -0.2 -0.4 -0.4 -0.6 -0.6 -0.6 -0.3 0.0 0.3 0.6 -0.6 -0.3 0.0 0.3 0.6 Bias (V) Bias (V) Figure 4 Test of the uniformity of array units. a, Optical image of a testing module with samples mounted onto a home-made printed circuit board. b, Enlarged image for a local area with three quadrant arrays. c, Further enlarged image for an individual 2×2 quadrant array. d-g, One- by-one test of the photoelectric behavior for the four array units (i.e., from quadrant 1 to 4). Inset images show the illumination locations of the focused excitation laser. Photocurrent (mA) Photocurrent (mA) Figure 5 Light Si (n-doped) MoS a b -17 -3 N =3x10 cm (pristine) 6μm 6μm - Φ MoS MoS E V + SiO Si c e g 6 Sensitivity (A/W) 5 10 -1 10 0.15 -2 0.12 10 -0.5 0.0 0.5 15 MoS /Si heterojuction 0.09 1 0.06 0.03 Dark 0.00 -1 546 nm 20 40 60 80 100 -2 -1 0 1 2 300 400 500 600 700 Light power (%) Bias (V) Wavelength (nm) d f h 0.15 500 nm 0 650 nm 450 nm 0.10 550 nm MoS /Si 400 nm 450 nm 0.05 350 nm V = 0.2 V OC 350 nm -5 J = 4.7 mA/cm SC 300 nm 0.00 0.0 0.1 0.2 0 20 40 60 80 100 0 50 100 150 Bias (V) Power (%) Time (ms) Figure 5 Test of the feasibility of the subsidence integration technique to other 2D crystals. a, Optical images for a typical MoS /silicon diode before and after SiO etching. b, Diagram of the 2 2 ++ energy level alignment of the MoS /silicon diode, which is actually an n/n heterojunction with small barrier heights (Φ and Φ ). c, Semi-logarithmic plot of the I-V curves under both dark C V (black dots) and light (red circles) conditions. d, Corresponding linear plot of the I-V curve. e, Contour plot of photoelectric sensitivity versus wavelength and light power. f, Sensitivity as a function of light power at different wavelength values from 350 to 650 nm. The devices also show negligible saturation in photoresponse within experimental power range. g, Estimated EQE for different wavelengths from 320 to 700 nm. h, Modulation of photocurrent by varying the excitation wavelength. Current (mA/cm ) Current (mA/cm ) Sensitivity (A/W) Wavelength (nm) Photocurrent (nA) Quantum Efficiency (%) Supporting Information Nano-Subsidence Assisted Precise Integration of Patterned Two-Dimensional Materials for High-Performance Photodetector Arrays *,1,2,5,6 1 1 1 1 Song-Lin Li, Lei Zhang, Xiaolan Zhong, Marco Gobbi, Simone Bertolazzi, 3 3 3 2 4 4,5,6 Wei Guo, Bin Wu, Yunqi Liu, Ning Xu, Weiyu Niu, Yufeng Hao, Emanuele *,1,§ *,1 Orgiu, Paolo Samorì University of Strasbourg, CNRS, ISIS UMR 7006, 8 allée Gaspard Monge, F-67000 Strasbourg, France; School of Electronic Science and Engineering, Nanjing University, Nanjing 210023, China; Beijing National Laboratory for Molecular Sciences, Institute of Chemistry, Chinese Academy of Science, Beijing 10086, China; College of Engineering and Applied Sciences, Nanjing University, Nanjing 210023, China; National Laboratory of Solid State Microstructures, Nanjing University, Nanjing 210093, China; Collaborative Innovation Center of Advanced Microstructures, Nanjing University, Nanjing 210093, China; Present address: Institut national de la recherche scientifique (INRS), EMT Center, 1650 Blvd. Lionel-Boulet, J3X 1S2 Varennes, Canada Address correspondence to sli@nju.edu.cn (S.L.L), emanuele.orgiu@emt.inrs.ca (E.O.), samori@unistra.fr (P.S.) Table of Content 1. Etching rates of SiO at different interfaces S2 2. Nano-subsidence integration S5 3. Intrinsic mobility and contact resistivity of pristine CVD graphene S9 4. Effect of TFSA doping on CVD graphene S11 5. Effect of HNO doping on mechanically exfoliated graphene S12 6. Refractive indices of candidate antireflection capping layers S13 7. Design of MoO antireflection layer S14 8. Effect of barrier height (Φ ) on V S16 B oc 9. Fit of series resistance S17 10. Performance as photovoltaic devices S18 11. Output power and linearity of monochromatic light source S19 S1 1. Etching rates of SiO2 at different interfaces For making 2D flake/Si junction with nano-subsidence method, there are three types of SiO interfaces deserved to consider during the SiO etching: 2D flake/SiO , 2 2 2 electrode/SiO , and resist mask/SiO . The first one is the desired interface for the 2 2 penetration of SiO etchant (BOE solution) to remove the SiO underneath the 2D 2 2 flake, while the latter two are not desired. Hence, the lateral etching rates for the latter two should be minimized. We found that the factor to determine the lateral etching rate of the material/SiO stacks is the chemical bonds formed between the top capping layer and the bottom SiO . In general, the rate is small when there are chemical bonds (Cr/SiO , resist mask/primed SiO ) while it becomes large when no bonds are present 2 2 (graphene/SiO , Au/SiO , resist mask/unprimed SiO ). Since there are no chemical 2 2 2 bonds formed between the 2D flake/SiO stacks, the lateral etching rate is rather large. For the electrode/SiO stacks, an adhesion metal layer such as chromium is very necessary to minim S1: iz e E tth che in g de ra trimenta tes of SiOl a late t difrfa el etc rent in hi te ng rfaces of the SiO under electrodes. Graphene/SiO Au/SiO 2 2 by 2 min. by 2 min. Etched by 2 min. c c' b b' a a' CVDG13_6etch_24.jpg G15H2 1L 5L 40 μm 10 μm 10 μm Resist (Cr)/SiO MS28_dev3_10: Lateral etching by 35 min. Capping layer Etch Cr 35min d d' SiO 3L 1L MS28rmv_J Etched by 1 min. 0.1 e' 10 μm G./SiO2: fast etching rate of 20 μm/min Au/SiO2: fast etching rate of 5 μm/min Cr/SiO2: slow etching rate of 0.08 μm/min 13 μm Figure S1 Etching rates of SiO underneath different capping layers. a-e, Optical images of devices just before SiO etching; a'-e', Corresponding images for devices after etching. The dashed black lines and black arrows indicate the area of graphene and etching directions, respectively. The dashed blue line and blue arrows in panel d' denote the patterned resist windows for etching and the direction of etching progression of the resist mask, respectively. a, graphene capped SiO2; b and c, Au capped SiO2; d and e, resist and Cr capped SiO2. f, Estimated etching rates for SiO2 capped by four types of materials (graphene, Au, mask resist and Cr). Inset: Diagram of lateral etching of SiO underneath a capping layer. Figure S1 shows the results of a comparative experiment where the etching rates of SiO at different interfaces (i.e., graphene/SiO , Au/SiO , resist mask/SiO and 2 2 2 2 S2 Graphene Au Resist Cr Etching rate of SiO (m/min.) 2 Cr/SiO2) are measured. The panels a-e show images of the samples before etching (etching windows to be exposed are visible); the panels a’-e’ show the images after etching. The dashed lines and black arrows indicate the area of graphene and etching directions, respectively. It is well known that there is only simple physical contact (van der Waals interaction) between either graphene or pure gold electrode and SiO (i.e., graphene/SiO and Au/SiO ), where no chemical bonds form, and thus the lateral 2 2 etching rate of SiO is high. Within 2 minutes the etching length could reach as much as 40 and 15 μm at the interfaces of graphene/SiO and Au/SiO , respectively. On the 2 2 contrary, there are strong chemical bonds between Cr and SiO or between resist mask and HMDS primed SiO surface; hence the etching rates for them are as low as ~0.1 and ~0.15 μm/min, respectively. By constant soaking in HF solution of 35 minutes, the etching lengths of SiO are only ~3 and 5.2 μm in cases of Cr and resist mask capping (panels d and d’). Within the normal etching time of about 1.5 min, the unwanted etching lengths are 200-300 nm for the graphene underneath the Au/Cr electrode and resist mask (panels e and e’); the detrimental etching of SiO is negligible. There is also potential risk of formation of low resistive pathways caused by the collapse of the electrode/2D crystal bilayer. However, we found that there is some tolerance in experiment. First, the work function of the Cr/Au electrode (1 nm Cr, 50 nm of Au) is relatively high, mainly following the thick Au layer, and it would form a Schottky junction for the trilayer structure electrode/graphene/n doped silicon. Hence, no obvious low resistive pathway/connection appears even in the event of a small-area bilayer collapse. Second, as an electronic effect of the collapse, the contacting area results in the increase of unfavorable shunt resistance in the circuit loop of photodiodes, which may deform the I-V curve or short-circuit the devices, depending on the magnitude of the shunt resistance. In our experiment, we observed that most devices remain electronically functional with 2-3 μm over etching. The stopping point of etching progression is just the boundary of the 2D crystals, outside which the Cr adhesion layer is strongly bonded to underlying SiO and results in negligible lateral etching rate of this area, as shown by the dashed line in Fig S1 e and e’. Panel f lists the lateral etching rates for the three interfaces. It is shown that the etching rate can vary by 2 orders of magnitude depending on the interface condition i.e., whether chemical bonds can be formed at the interfaces. For instance, depositing S3 Au or graphene onto SiO2 will not create chemical bonds between Au (graphene) and SiO , which results in a high lateral etching rate. Instead, depositing Cr onto SiO 2 2 creates an additional Cr-O bonds (in presence as chromium oxide) between Cr and SiO , which leads to a low lateral etching rate. Since the processing step of SiO 2 2 etching is placed in the last in our nano-subsidence technique, a precise control of the etching rate of SiO is critical for the overall fabrication resolution. We verified that the addition of the adhesion layer (such as Cr, Ti) underneath the metallic electrode, which is translated as an adhesion layer between the electrode and SiO during etching (Figure 1b in the main text), can avoid the unfavorable etching of SiO and hence ensure our fabrication resolution. S4 FigS2: Yield of nano-indentation technique 2. Nano-subsidence integration a b c d e a' b' c' d' e' Q2 Q1 Q2 Q1 Q2 Q1 Q2 Q1 Q2 Q1 Q3 Q3 Q3 Q3 Q4 Q4 Q3 Q4 Q4 Q4 f g h i Good Failed f' g' h' i' Q2 Q1 Q2 Q1 Q2 Q1 Q2 Q1 Q3 Q4 Q3 Q4 Q3 Q3 Q4 40 μm Q4 Figure S2 Yield of device fabricated by the nano-subsidence technique. a-i, Optical images of the four-quadrant photodetector before nano-subsidence; a'-i', Corresponding images for devices after applying the nano-subsidence. The blue and orange dashed lines represent the good and failed quadrants, respectively. Among the 36 quadrants, 34 of them are good. Although slightly fierce operations (such as water scouring to graphene during rinse after HF etching) are employed in sample fabrication, most graphene pieces stick well to the underlying Si layers. Figure S2 show the optical images for the 9 arrays of the four-quadrant devices before and after the subsidence processing. Here, we take one quadrant as an individual sample and the quadrants with visible graphene folding, scrolling or rupture are counted as the failure. We estimated the sample yield as high as 94.4% (34 out of 36 quadrants), which indicates the high reliability of our nano-subsidence technique. By using conventional photolithography, we also fabricated large scale arrays with the nano-subsidence and conventional integration methods, respectively, to enable direct comparison of the two methods. The main results are listed in Table S1 with the superior figures of merit marked in bold. The reported values provide unambiguous evidence that our nano-subsidence integration method outperforms in parameters such as sample yield, probability of strain accumulation, surface roughness of graphene/silicon, and time of air exposure of bare silicon, although both integration S5 methods result in comparable peak photoresponsivity. We have recorded AFM images of the surface following nano-subsidence and conventional integration techniques. The results are displayed in Figure S3 below. We used the root mean square (RMS) roughness in order to gain a quantitative insight into the graphene morphology, and to evaluate the cleanness of the graphene/silicon interfaces. The left panel, displaying devices obtained using our nano-subsidence integration method, reveals a cleaner graphene interface with lower RMS roughness of ~0.52 nm, compared to the right panel which displays interfaces obtained using conventional method, the latter exhibiting a RMS roughness of ~0.84 nm. Table S1 Comparison of different parameters of the two integration methods. Better values are indicated in bold. Nano-subsidence Conventional method method Sample yield ~96% ~88% Probability of strain accumulation <1% >8% Surface roughness of graphene/silicon 0.52 nm 0.84 nm Time of air exposure of bare silicon >3 hours < 60 seconds Peak photoresponsivity 0.35 A/W 0.37 A/W First, the 8% higher yield ratio (96% vs. 88%) is attributed to the effect of electrode anchoring, which stabilizes one of the three edges of the slidable graphene flakes during subsequent microfabricaton processing. Second, the greatly reduced probability of strain accumulation (from 8% to 1%) can be ascribed to the different integration process. In the conventional way, entire pieces of graphene sheets are transferred and closely attached to the whole substrates; no more chance for strain release after heat dry. Instead, in our new technique, the strain accumulated in the first transfer process can be well released in the process of nano-subsidence when SiO is gradually etching way. As mentioned above, except for the anchored edge (Figure 1c, bottom panels), there are two edges of the graphene flakes floated in the etchant and the strain can be well released during the subsidence to bare silicon. Third, the difference in interface cleanness (surface roughness, Figure S3) of graphene/silicon (0.52 vs. 0.84 nm) likely arises from the specific device S6 microstructure as depicted in the cartoon. The devices from nano-subsidence generally feature a less rough underlying support for graphene, which facilitates the expulsion of liquids and soluble impurities during heat/vacuum dry. Instead, the devices fabricated following the conventional method are predefined with silicon cavities, which therefore tend to trap soluble impurities and to contaminate the graphene/silicon interface after heat dry. Trapping of impurities led to an increase of surface roughness. Other bonus from the nano-subsidence technique includes minimized time of air exposure of bare silicon and preserved fresh silicon interface, which offer great flexibility in further interface engineering between silicon and 2D crystals. We also need to clarify the device performance from the two integration techniques, which are comparable, since the peak photoresponsivity reaches 0.35-0.37 A/W when other device parameters are fully optimized. This indicates that the device performance has little to do with the integration methods. Finally, it is worth noting that the yield ratio of the MoS junctions is slightly higher than graphene junctions, reaching nearly 97%, because the MoS flakes adopted are generally thicker and more rigid than graphene, leaving them little chances to rupture. Nano-subsidence integration Conventional integration Heat dry Heat/vacuum dry Graphene Graphene Bare Si Bare Si Liquid expelled Liquid trapped Figure S3 Schematics of formation of interfacial residues between graphene and bare silicon and the corresponding surface roughness of graphene after SiO removal as seen with AFM. Left and right panels are for the nano-subsidence and conventional integration techniques, respectively. S7 Since thick 2D materials would become rigid and unbendable, the conformal step coverage of thick 2D materials on patterned Si substrates would be difficult and there are certain thickness limits for using the nano-subsidence integration. From our data, we can conclude that the lower thickness limit for subsidence integration is 4 layers for graphene and 5 layers for MoS (Figure 5a), respectively. Another factor alleviating the requirement on thickness limit is the gentle slope of ~16° formed at the step, as confirmed by the AFM profile and depicted by the cartoon (Figure S4, right panel). The gentle, rather than sharp, slope normally facilitates the conformal step coverage of 2D films on the patterned steps. Real profile of 2D film 2D film on patterned step Minimized strain Step 84 nm 16° ~300 nm Subsided graphene 84nm Subsided graphene covering patterned step Figure S4 Left: SEM images for junctions with well-subsided graphene. Right: AFM image near a patterned edge of the graphene junction. In both images, no clear traces of strain induced ripples are observed. S8 S3: Intrinsic mobility and contact resistivity of pristine CVD graphene 3. Intrinsic mobility and contact resistivity of pristine CVD graphene 0.6 L = 4.1 m 0.4 V ~ 17 V 10.2 m CNP L = 19.4 m 0.2 0 0.0 -10 0 10 20 30 40 -10 -5 0 5 10 V (V) V (V) g g 1.0  = 2.2 mS, V = 0 2 -1 -1 V = -10 V  = 2800 cm V s 0.8 2 0.6 0.4 V = 10 V 0.2 Pristine 0 0 0.0 0 5 10 15 20 -1 -10 0 -5 -5 0 0 5 5 10 10 V (V) Channel length (m) Figure S5 Extracting intrinsic carrier mobility and contact resistivity of pristine CVD graphene. a, A typical transfer curve of the pristine CVD graphene in air, where the charge neutrality point (V ) is normally at V around 15-17 V. Here the thickness of SiO CNP g 2 dielectric is 90 nm and V = 0.1 V. b, Transfer curves for graphene channels with different ds channel lengths. Inset: Optical image of the device for TLM measurement. c, TLM fit to extract mobility and contact resistance. d, Left axis: Intrinsic transfer curve after ruling out the contact effect, which can be used to extract intrinsic mobility. Right axis: Extracted contact resistivity versus gate voltage. The CVD graphene was grown on copper foils and its quality was carefully checked. The intrinsic carrier mobility and contact resistance were estimated by the conventional transfer-length measurement (TLM). In the ambient environment the graphene is p-doped by oxygen and humidity, which shifts the charge neutrality point (V ) to around V = 15-17 V, as shown in Figure S5a. To estimate the hole (the CNP g leading carriers passing graphene in this study) mobility of the CVD graphene, we used the data in the V range from -10 to 10 V. As shown in the inset of Figure S5b, four electrodes with varied spacing were defined on a well etched graphene ribbon, where three graphene channels were defined with channel lengths (L) of 4.1, 10.2 and 19.4 μm, respectively. Figure S5b shows the transfer curves of the three channels S9 Resistance* Width (cm) Conductance (mS) Conductance (mS) Square conductivity (mS) Contact resistivity (Wcm) where the gate voltage (Vg) is changed from -10 to +10 V. All channels exhibit p-doping behavior due to the oxygen doping effect in air. Figure S5c shows the TLM plots at different V values at a step of 1V. The intercept and the slope of the linear fits of the data reflect the information of contact resistance and intrinsic channel conductivity (Figure S5d). We extracted an intrinsic carrier mobility (μ) of 2800 2 -1 -1 cm V s and a zero-bias square conductivity (σ) of 2.2 mS, suggesting high quality of the CVD graphene used. The extracted contact resistivity of Cr/Au electrode to graphene is also plotted to the right Y axis in Figure S5d. It increases from 0.35 to 0.8 Ω·cm when V changes from -10 to 10V, which is about 10 times higher than that of the Pd/Au contacts (0.02-0.04 Ω·cm). The less perfect contact is likely responsible for the large series resistance of the devices (discussed below). S10 S4: Effect of TFSA doping on CVD graphene 4. Effect of TFSA doping on CVD graphene a b 0.8 TFSA: 0.6 Pristine 0.4 TFSA 0.2 After TFSA doping 0.0 -10 -5 0 5 10 V (V) After TFSA doping Pristine  = 8.8 mS, V = 0 2 -1 -1  = 760 cm V s  = 2.2 mS, V = 0 -6 2 -1 -1  = 2800 cm V s Pristine After TFSA doping -12 -10 -5 0 5 10 0.0 0.2 0.4 0.6 V (V) Bias (V) Figure S6 Effect of TFSA doping on electronic performance of CVD graphene and related photodiodes. a, Diagram of TFSA doping and Fermi level engineering of graphene. b, Variation of contact resistivity by doping. c, Change of channel conductivity and carrier mobility by doping. d, Improvement of photoresponse after doping. Figure S6a show the diagram of engineering the Fermi level of graphene. Since TFSA is a strong electron-drawing molecule, upon spinning coating it on graphene, it is expected to highly dope graphene and downshift the Fermi level via charge transfer. Electronically, the TFSA doping has three effects: 1) It reduces the contact resistivity to 0.2 Ω·cm in most Vg regime (Figure S6b); 2) It increases σ of graphene from 2.2 to 2 -1 -1 8.8 mS at V =0; 3) It degrades from 2800 to 760 cm V s , because the TFSA molecules are randomly distributed charges above graphene, which serves as additional scattering centers. Although the third effect is detrimental to photoresponse, the residual mobility remains high enough to support the photocarrier transport. After TFSA doping, the overall device performance is much improved by the first two favorable effects. A large increase on both short-circuit current (J ) and open-circuit sc voltage (V ) is observed (Figure S6d). oc S11 Square conductivity,  (mS) Current density, J (mA/cm ) Contact resistivity (cm) S5: Effect of HNO doping on mechanically exfoliated graphene 5. Effect of HNO3 doping on3 mechanically exfoliated graphene st nd rd th 1 : Pristine 2 : HNO vapor 40s 3 : 150°C, 10min 4 : + HNO vapor 20s 3 3 b 10 μm 2L 3L + 1L G18-A 2nd nd 2 : 1000 Ω/☐ 4th: 1400 Ω/☐ 4th 1st rd 3 : 1400 Ω/☐ 2nd 3rd 3rd st 1st 1 : 2000 Ω/☐ -6 4th 1st 10 mv/ 6 uA = 2 kΩ 2nd 3rd 10 mv/ 12 uA = 1 kΩ -12 4th -10 0 10 20 30 40 -0.5 0.0 0.5 • conductivity ↑ V (V) Bias (V) • mobility ↓ Figure S7 Effect of HNO doping on electronic performance of mechanically exfoliated graphene and related photodiodes. a, Diagram of different doping levels. b, Transfer curves at different doping levels. c, Variation of photoresponse curves at different doping levels. Figure S7 show sequential experiment results of HNO doping on an individual device at four stages: 1) Pristine; 2) HNO vapor exposure by 40 s; 3) Heated at 150 °C by 10min; 4) Re-exposure of HNO vapor by 40 s. The schematic diagrams are shown in Panel a. Panel b shows the transfer curve at the four conditions, exhibiting quite similar trends with TFSA doping, that is, σ increases and μ decreases upon doping (Stage 1 to 2), reflecting the effect of charge transfer and effective doping. In the stage 3 of heating (150 °C, 10min), σ decreases and μ is unchanged, which means degradation of contact. This is consistent with the S-shape photocurrent curve (green line, panel c). In the stage 4 of re-exposure of HNO vapor, no large improvement in σ but further μ degradation are seen, indicating the saturation in doping. Further exposure to HNO vapor will only increase the defect density in graphene and there is no recovery of the photocurrent curve (blue line, panel c) because HNO can produce carbon vacancies by reaction with graphene. S12 Current of graphene (A) Current density, J (mA/cm ) 6. Refractive indices of candidate antireflection capping layers TiO PMMA MoO 2 3 SiO ZnO Si N 2 3 4 MgF SiC sqrt(n ) 2 si 400 500 600 700 800 Wavelength (nm) Figure S8 Refractive index values for several candidate antireflection capping layers and the ideal values (𝑛 = 𝑛 𝑛 ). 𝑟𝑎𝑖 S13 Refractive index 𝑠𝑖 𝐴𝑅 7. Design of MoO3 antireflection layer S6: Design of MoO antireflection layer a b 120 120 Theoretical (wo. graphene) Theoretical (wi. graphene) 100 100 80 80 60 60 wo. MoO wo. MoO 3 3 40 40 50 nm MoO 50 nm MoO 3 3 80 nm MoO 80 nm MoO 20 20 3 3 110 nm MoO 110 nm MoO 3 3 0 0 400 600 800 1000 400 600 800 1000 Wavelegnth (nm) Wavelegnth (nm) 120 120 Theoretical Experimental 100 100 55 nm MoO AR 80 55 nm MoO AR wo. MoO AR wo. MoO AR 3 40 40 1-R EQE 300 400 500 600 700 800 300 400 500 600 700 800 Wavelegnth (nm) Wavelegnth (nm) Figure S9 Design and application of MoO antireflection layer. a, Calculated absorption (1-R) for different AR thicknesses without placing graphene. b, Corresponding results with placing graphene. No noticeable difference can be seen between a and b. c, Calculated absorption (1-R) curves for zero and 55 nm MoO AR. d, Corresponding experimental data on absorption (1-R) and EQE. The application of antireflection (AR) layers is a common technique to increase the device photoresponse. Theoretical calculation was used for rational design of the thickness of the MoO AR layers. We first identified that the ultrathin layers (such as graphene and TFSA) have negligible effect on the optical reflection. Figure S9 a-b compare the calculated absorption (1-R) curves with and without graphene in the layered devices. As can be seen, the 1-R curves are nearly identical at each MoO thickness. Hence, for simplification we neglected the ultrathin layers of graphene and TFSA in later calculations. In Figure S9b, one can find that a MoO layer with thickness between 50-80 nm can enhance the 1-R values in most visible range. In experiment, we used 55 nm MoO . Figure S9c plots the calculated 1-R curves for devices with bare and 55 nm MoO S14 1-R (%) 1-R (%) 1-R and EQE (%) 1-R (%) AR layers. Evidently, upon depositing the MoO3 AR layer, the 1-R values are enhanced in the whole visible regime. In particular, the 1-R can be enhanced from 60% to 100% at 450 nm due to the destructive interference in reflection. We also determined the real 1-R curve with reflection spectroscope from 400 to 800 nm (blue and red lines, Figure S9d) and calculated the external quantum efficiency (EQE, blue and red circles, Figure S9d) from 300 to 700 nm. Both values (1-R and EQE) are quite close at each wavelength, implying a nearly unity internal quantum efficiency (IQE = EQE/(1-R)) and a high interface quality of our devices fabricated with the nano-subsidence technique. Overall, the experimental curves shown in panel d agree reasonably with the calculation shown in panel c. S15 S8: Effect of graphene work function on V 8. Effect of barrier height (ΦB) on Voc oc a b Graphene/Si Graphene/Si TFSA doped TFSA + MoO MoO TFSA TFSA Graphene/Si 2 Graphene/Si Exp. 0 Fit 0.1 0.2 0.3 0.1 0.2 0.3 Bias (V) Bias (V) 0.84 Graphene/Si OC TFSA + MoO + TFSA 0.81 0.3 0.78 TFSA MoO 0.75 TFSA -6 0.45 0.50 0.55 V (V) Graphene/Si OC -12 0.0 -18 0.1 0.2 0.3 0.0 0.1 0.2 0.3 0.4 0.5 Bias (V) Bias (V) Figure S10 Dependence of open-circuit voltage Voc on barrier height ΦB. a-c, Fits of barrier height by thermionic-emission equation at varied doping levels. Insets: Diagram of doping schemes. d, Photoresponse curves at different doping levels where V changes accordingly. Inset: Plot of Φ and V at different oc B oc doping levels. We also investigated the relation of barrier height (Φ ) and V . Φ was tuned by B oc B changing the work function of graphene via doping levels. Three doping levels were achieved by consequently applying TFSA, MoO3, and a second TFSA; the doping schemes were shown in the insets of Figure S10 a-c, respectively. The values of Φ were estimated by fitting the I-V curves with the thermionic-emission equation 𝛷 𝑉 ∗∗ 2 𝐽 = A 𝑇 exp ( − ) [exp ( − ) − 1] dark -2 -2 where 𝐽 is the dark current and A**=252.4 A·cm ·K is the Richardson constant dark along the <100> direction of silicon. The fits are represented by the red lines in Figure S10 a-c, which agree well with the experimental data. The extracted Φ are 0.786, 0.770, and 0.825 eV for the above doping levels, corresponding to V of 0.495, 0.475, oc and 0.548 V, respectively (Figure S10d). It is found that V exhibit a linear oc dependence on Φ , as shown in the inset of Figure S10d. S16 Current (A/m ) Current (A/m ) 2 2 Photocurrent (mA/cm ) Current (A/m ) Barrier height (eV) 𝑛𝛽 9. Fit of series resistance a b 0.2 Rectification ratio = 10 -1 -2 -3 -4 0.1 -5 R = 1.9 k,n = 2.23 -6 -7 -1.0 -0.5 0.0 0.5 1.0 0 30 60 90 V (V) Current, I (A) Figure S11 Fit of series resistance with the transformed thermionic-emission equation. a, Semi-logarithmic plot of the I-V curves of a TFSA doped graphene/silicon junction under dark condition, where a high rectification ratio of 10 is observed. b, Fitting the I-V curve to extract the junction parameters: series resistance R and ideality factor n. Inset: Optical image of the corresponding device before SiO etching. The series resistance (R ) of the TFSA doped device was fitted with the 3,4 transformed thermionic-emission equation d𝑉 𝑛 = 𝑅 𝐼 + ( ) d ln𝐼 𝛽 where n is the ideality factor and 𝛽 = 𝑒 / is the inverse thermal voltage. Figure S11 show the experimental data and related fit. The values of R and n are estimated to be 1.9 kΩ and 2.23, respectively. Given the dimension of the device (100×100 μm , inset of Figure S11b), the normalized R is 0.19 Ω/cm , consistent with previous reports. S17 Current, I (A) dV/d(lnI) (V) 𝑘𝑇 Filling Factor Filling Factor Filling Factor Filling Factor 10. Performance as photovoltaic devices S9: Performance as photovoltaic devices 8.3% 36% 520 nm a 520 nm b Graphene/TFSA/MoO Graphene/TFSA 3 Si Si TFSA → doping graphene 55 nm MoO → antireflection layer 0 1.0 0 1.0 ID: CVDG14_F ID: CVDG14_F (0.0106 mm , TFSA) (0.0106 mm , MoO AR) 2 0.8 0.8 520 nm, 44.8 mW/cm -5 520 nm, 44.8 mW/cm V = 0.545 V OC V = 0.578 V -5 OC 0.6 0.6 J = 11.3 mA/cm SC J = 15.6 mA/cm SC FF = 0.734 -10 FF = 0.769  = 10.1% 0.4  = 15.6% 0.4 -10 -15 0.2 0.2 -15 0.0 -20 0.0 0.0 0.2 0.4 0.6 0.0 0.2 0.4 0.6 Bias (V) Bias (V) AM1.5 AM1.5 Graphene/TFSA/MoO Graphene/TFSA 3 Si Si TFSA → doping graphene 55 nm MoO → antireflection layer 0 1.0 0 1.0 ID: CVDG14_F ID: CVDG14_F 2 2 (0.0106 mm , TFSA) (0.0106 mm , MoO AR) 2 0.8 0.8 AM1.5, 100 mW/cm AM1.5, 100 mW/cm V = 0.579 V OC V = 0.597 V -10 -10 OC 0.6 0.6 J = 22.5 mA/cm J = 25.9 mA/cm SC SC FF = 0.696 FF = 0.704  = 9.07%  = 10.9% 0.4 0.4 -20 -20 0.2 0.2 -30 0.0 -30 0.0 0.0 0.2 0.4 0.6 0.0 0.2 0.4 0.6 Bias (V) Bias (V) Figure S12 Comparison of photovoltaic parameters at different device configuration and illumination conditions. a, No AR layer under monochromatic illumination. b, Optimized AR layer under monochromatic illumination. c, No AR layer under AM1.5 illumination. d, Optimized AR layer under AM1.5 illumination. Figure S12 show the complete device performance as photovoltaic cells, characterized under different device configuration (with or without MoO AR layer) and illumination conditions (monochromatic illumination/ reduced power and standard AM1.5 condition). The detailed device parameters are summarized below. Device MoO3 Filling Photoconversion Illumination Voc Jsc No. (nm) factor, FF efficiency, η 1 0 520 nm, 0.545 11.3 0.734 10.1% 2 55 44.8 mW/cm 0.578 15.6 0.769 15.6% 3 0 0.579 22.5 0.696 9.07% Standard AM1.5 4 55 0.597 25.9 0.704 10.9% S18 2 2 Photourrent (mA/cm ) Photourrent (mA/cm ) 2 2 Photourrent (mA/cm ) Photourrent (mA/cm ) 11. Output power and linearity of monochromatic light source Forward Backward 0 0 300 400 500 600 700 0 20 40 60 80 100 Wavelength (nm) Setting power percentage (%) Figure S13 Output power and linearity of monochromatic light source employed in experiment. a, Output power as a function of light wavelength where the power peaks at 470 nm. b, Test of power linearity of the control system. Reference (1) Xia, F.; Perebeinos, V.; Lin, Y.-M.; Wu, Y.; Avouris, P., The Origins and Limits of Metal-Graphene Junction Resistance. Nat. Nanotechnol. 2011, 6, 179–184. (2) Sze, S. M.; Ng, K. K., Physics of Semiconductor Devices. 3rd edn., John Wiley & Sons, New Jersey, 2007. (3) Werner, J. H., Schottky Barrier and pn-Junction I/V Plots – Small Signal Evaluation. Appl. Phys. A 1988, 47, 291–300. (4) Shi, E.; Li, H.; Yang, L.; Zhang, L.; Li, Z.; Li, P.; Shang, Y.; Wu, S.; Li, X.; Wei, J.; Wang, K.; Zhu, H.; Wu, D.; Fang, Y.; Cao, A., Colloidal Antireflection Coating Improves Graphene-Silicon Solar Cells. Nano Lett. 2013, 13, 1776–1781. S19 Power (W) Real power (W)

Journal

PhysicsarXiv (Cornell University)

Published: Jun 24, 2023

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