Select All | Select None
You can now keep track of new articles from Journal of Embedded Computing on your personalized homepage!
The effectiveness of Instruction Reuse (IR) - a technique to eliminate redundant computations at run time - is limited by the fact that performance gain seldom exceeds 3% and is dependent on the criticality of instructions being "reused". In this paper, we focus on the power aspect of IR and...
Modern digital systems consist of a complex mix of computational resources, e.g. microprocessors, memory elements and reconfigurable logic. System partitioning - the division of application tasks onto the system resources - plays an important role for the optimization of the latency, area, power...
The set of frames exchanged in automotive applications must meet two constraints: it has to be feasible from a schedulability point of view and it should minimize the network bandwidth consumption. This latter point is important since it allows the use of low cost electronic components and it...
Power consumption is becoming one of the most important constraints for microprocessor design in nanometer-scale technologies. Especially, as the transistor supply voltage and threshold voltage are scaled down, leakage energy consumption is increased even when the transistor is not switching....
With the scaling of technology, leakage energy reduction has become increasingly important, especially for cache memories. Recent studies in drowsy instruction cache show that the leakage energy of the instruction cache can be significantly reduced with little performance degradation by...
Many applications commonly found in digital signal processing and image processing applications can be represented by data-flow graphs (DFGs). In our previous work, we proposed a new technique, extended retiming, which can be combined with minimal unfolding to transform a DFG into one which is...
A SuperH™ embedded processor core SH-X implemented in a 130-nm CMOS process running at 400~MHz achieved 720 MIPS and 2.8 GFLOPS at a power of 250 mW under worst-case conditions. It has a dual-issue seven-stage pipeline architecture, but reaches the 1.8 MIPS/MHz of the previous five-stage...
Indirect memory accesses, where a load is fed by another load, are ubiquitous because of rich data structures and sophisticated software conventions, such as the use of linkage tables and position independent code. Unfortunately, they can be costly: if both loads miss, two round trips to memory...
The trend of the networking processing is to increase the intelligence of the routers (i.e. security capacities). This means that there is an increment in the workload generated per packet and new types of applications are emerging, such as stateful programs. On the other hand, Internet traffic...
results per page
Save this article to read later. You can see your Read Later on your DeepDyve homepage.
To save an article, log in first, or sign up for a DeepDyve account if you don't already have one.
Sign Up Log In
To subscribe to email alerts, please log in first, or sign up for a DeepDyve account if you don't already have one.
Read and print from thousands of top scholarly journals.
Sign up with Facebook
Sign up with Google
Already have an account? Log in
To get new article updates from a journal on your personalized homepage, please log in first, or sign up for a DeepDyve account if you don't already have one.