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This column consists of selected traffic from the comp.arch newsgroup, a forum for discussion of computer architecture on Internet---an international computer network.
Typical implementation of sequential consistency in shared-memory systems requires each access to be delayed until the previous access in the same process completes. This is detrimental to system performance. This paper proposes a way of out-of-order execution in sequentially consistent...
This paper presents a memory model and architecture for synchronization of threads or tasks when accessing regions of virtual memory. Access control is defined on a memory region through a view that defines the size of access units and also the protocol in terms of a Finite State Machine (FSM)....
The architecture described in the following articel is a direct successor of µ-EP-1 (cf. 1) and was developed by the author and Robert Linden (Universität Bonn, FB Informatik). NICE is a 32-bit processor, utilizing a fixed instruction format, a register set of sixteen general purpose registers...
In this paper, we propose a new strategy (KORA-2) for the replacement of lines in cache memories. The algorithm is efficient and easily implementable. It is basically an extension of our previous work presented in 1-5. Key to our algorithm is to identify and discard inactive lines relatively...
Trace-driven simulation has been widely used by designers and performance analyst to study and evaluate performance of computer systems. The increasing complexity benchmarks combined with the relatively slow rate of detailed performance analysis has resulted in a widening gap between the size of...
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