Design procedure for multifinger MOSFET two‐stage OTA with shallow trench isolation effectVeldandi, Harikrishna; Rafi Aahmed, Shaik
2018 IET Circuits, Devices & Systems
doi: 10.1049/iet-cds.2017.0419
Nanoscale complementary metal–oxide–semiconductor (CMOS) circuit design extensively employs multifinger layout technique to alleviate the performance degrading parasitic and mismatch effects that are typically observed with single‐finger layout. However, a continuous increase in the number of fingers accompanied by a simultaneous decrease in their finger width could lead to the penalty of a higher degree of variation in the MOSFET's small‐signal parameters. It is due to the heightened shallow trench isolation (STI) stress that gets developed in such devices. The optimisation of circuit performance with the arbitrarily fixed number and width of fingers would be ambiguous. In this work, an analysis of current–voltage (I–V) characteristics of a MOSFET as a function of number of fingers has been proposed. It was found that both the drain current and gate transconductance get affected by the number of fingers. The authors proposed a Miller‐compensated two‐stage [operational transconductance amplifier (OTA)] and common source amplifier by considering STI effect. It is also found that the parameters of the proposed design matched well with the set of desired specifications. Also, the area of multifinger MOSFET OTA is lowered by up to 60% relative to that from the conventional. All post‐layout simulations were performed using standard UMC 65 nm CMOS technology.
Mixed‐signal demodulator for IEEE 802.15.6 IR‐UWB WBAN energy detection‐based receiverJajodia, Babita; Mahanta, Anil; Rafi Ahamed, Shaik
2018 IET Circuits, Devices & Systems
doi: 10.1049/iet-cds.2017.0350
A mixed‐signal baseband demodulator for IEEE 802.15.6 impulse‐radio ultra‐wideband (IR‐UWB) wireless body area network (WBAN) energy detection‐based receiver is presented. It considers M‐ary pulse position modulation (PPM) signalling format conforming to the IEEE 802.15.6 WBAN standard. The demodulator utilises ‘integrate‐and‐digitise’ approach employing simple mixed‐signal circuits. The design is implemented in 0.18 μm CMOS technology operating at 1.8 V supply. The demodulator consists of a mixed‐signal windowed integrator, a single‐ended successive approximation register analogue‐to‐digital converter followed by a digital back‐end. Further, its performance evaluation is carried out for 2‐ary and 16‐ary PPM signalling in different WBAN channels.
Hardware implementation and VLSI design of spectrum sensor for next‐generation LTE‐A cognitive‐radio wireless networkMurty, Mahesh S.; Shrestha, Rahul
2018 IET Circuits, Devices & Systems
doi: 10.1049/iet-cds.2017.0292
This paper presents reconfigurable and hardware‐efficient VLSI architecture of time domain cyclostationary‐feature detector (TCD) for spectrum sensing in the cognitive‐radio wireless network. It incorporates new architecture for autocorrelator that supports the entire range of subcarriers used by orthogonal frequency division multiplexing signals compliant to 4G LTE‐Advanced wireless network. A novel scheme of overflow/underflow protection is proposed for the coordinate rotation digital computer engine of TCD. Additionally, hardware‐efficient techniques have been introduced for the multiply‐&‐accumulate and accumulator architectures of suggested TCD design. Real‐world signals are captured using universal software radio peripheral devices and are fed to its FPGA prototype. An application specific integrated circuit synthesis and post‐layout simulation of the proposed detector have been performed using 65 nm‐CMOS technology and it occupies 0.32 mm2 of core area and consumes total power of 18.5 mW at 100 MHz clock frequency. In comparison with the state‐of‐the‐art works, the proposed detector requires 34 and 93% lesser hardware resource and memory, respectively
Precision analysis with analytical bit‐width optimisation process for linear circuits with feedbacksLamini, El‐Sedik; Tagzout, Samir; Belbachir, Hacène; Belouchrani, Adel
2018 IET Circuits, Devices & Systems
doi: 10.1049/iet-cds.2017.0514
Finding the best possible word length to accuracy trade off seems to be an obvious design task. However, the literature and carful design reviews show that word lengths are often overestimated to put the data accuracy at the safe side. This study proposes a mathematical process to balance that trade off. It describes an analytical optimisation technique that considers every interconnection and it shows clear improvement with respect to published results. To allow reproducibility of their work, detailed procedures are provided. Implementation results are presented for different configurations of infinite impulse response filters. More, the impact of the proposed bit‐width optimisation on the filter poles and zeros is provided to show the effectiveness of the proposed solution. Their solution provides overall improvement going up to 17% of the circuit's area with respect to existing methods. The proposed technique for uniform fractional bits allocation runs in a negligible time independently of the targeted accuracy.
Symptom reliability: S‐parameters evaluation of power laterally diffused‐metal–oxide–semiconductor field‐effect transistor after pulsed‐RF life tests for a radar applicationBelaïd, Mohamed Ali
2018 IET Circuits, Devices & Systems
doi: 10.1049/iet-cds.2018.0005
This paper treats the s‐parameter performance degradation by hot electron induced for N‐MOSFET devices used in radar applications. This study is relevant for devices operating in the RF frequency regime. The power LD‐MOSFET device (0.8 µm channel length, Gate oxide thickness 0.065 µm and 2.2 GHz) are designed and fabricated. Subsequently, life tests in pulsed RF cause, after ageing, the electrical behaviour and its relation with charge trapping at the interface are presented and discussed. Unlike all other current methods, a complete evaluation of S parameters is carried out to obtain key information concerning the defects location. The s‐parameter performance degradation can be explained by the transconductance and the miller capacitance move, and by the leakage current augmentation IG, which is shown by hot‐carrier event from the Si/SiO2 interface state generation and/or in a build up of negative charge. Also, the degradation can be predicted by the experimental correlation of RF and dc performance shifts, favour by the measurement of dc performance or initial leakage current. The analysis accompanied proves that the s‐parameters shift by hot electron induced and should be taken into consideration in the design. Through physical processes of ATLAS‐SILVACO simulations these degradation phenomena are located and confirmed
Spintronic memristor synapse and its RWC learning algorithmChen, Jing; Duan, Shukai; Dong, Zhekang; Wang, Lidan
2018 IET Circuits, Devices & Systems
doi: 10.1049/iet-cds.2017.0427
As one of the most widely used memristor models, the spintronic memristor has become a promising candidate for the electronic synapse. Non‐volatility, nanoscale geometries, binary data and multi‐level information storage make the circuit simpler and consume less electricity. In this study, a new spintronic memristor synaptic circuit is proposed which can realise positive, zero and negative weights successfully. Furthermore, the circuits of the presented synaptic‐based neuron and compact neural network are designed and an improved random weight change (RWC) algorithm is proposed. Compared with the traditional RWC algorithm, it has faster training speed and less training error. In addition, the neural network is applied to data prediction, the result of which is closer to real data. Finally, the correctness and effectiveness of the proposed network are verified via a series of computer simulations.
Rigorous mathematical model of through‐silicon via capacitanceKim, Kibeom; Kim, Jedok; Kim, Hongkyun; Ahn, Seungyoung
2018 IET Circuits, Devices & Systems
doi: 10.1049/iet-cds.2017.0157
Through‐silicon vias (TSVs) are a key technology for three‐dimensional integrated circuits. As the integration of circuits increases, high temperature has a greater effect on the performance of the TSV interconnections. The metal–oxide semiconductor (MOS) effect is one of the most important temperature‐dependent characteristics of a TSV. This study introduces the mathematical model of a TSV to predict the MOS effect more accurately. The thermal effect that varies due to the change in the TSV capacitance and depletion region can be modelled by the non‐linear the Poisson equation including mobile charge carriers. In procedures to solve this equation, the proposed method considers not only the thermal effect of intrinsic carrier concentration and silicon bandgap energy but also the shift effect of the flat band voltage due to the Si–SiO2 interface charges. In addition, since it considers the minority carrier generation rate, which is dependent on the change of gate voltage, the MOS effect in a TSV can be explained more accurately using equations derived from these procedures. To verify the proposed mathematical model, comparison with the numerical method is carried out, and these results show that the proposed method is very accurate in explaining the MOS effect in a TSV.