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Huang, Tian; Gan, Guisheng; Liu, Cong; Ma, Peng; Ma, Yongchong; Tang, Zheng; Cheng, Dayong; Liu, Xin; Tian, Kun
2023 Microelectronics International
This paper aims to investigate the effects of different ultrasonic-assisted loading degrees on the microstructure, mechanical properties and the fracture morphology of Cu/Zn+15%SAC0307+15%Cu/Al solder joints.Design/methodology/approachA new method in which 45 μm Zn particles were mixed with 15% 500 nm Cu particles and 15% 500 nm SAC0307 particles as solders (SACZ) and five different ultrasonic loading degrees were applied for realizing the soldering between Cu and Al at 240 °C and 8 MPa. Then, SEM was used to observe and analyze the soldering seam, interface microstructure and fracture morphology; the structural composition was determined by EDS; the phase of the soldering seam was characterized by XRD; and a PTR-1102 bonding tester was adopted to test the average shear strength.FindingsThe results manifest that Al–Zn solid solution is formed on the Al side of the Cu/SACZ/Al joints, while the interface IMC (Cu5Zn8) is formed on the Cu side of the Cu/SACZ/Al joints. When single ultrasonic was used in soldering, the interface IMC (Cu5Zn8) gradually thickens with the increase of ultrasonic degree. It is observed that the proportion of Zn or ZnO areas in solders decreases, and the proportion of Cu–Zn compound areas increases with the variation of ultrasonic degree. The maximum shear strength of joint reaches 46.01 MPa when the dual ultrasonic degree is 60°. The fracture position of the joint gradually shifts from the Al side interface to the solders and then to the Cu side interface.Originality/valueThe mechanism of ultrasonic action on micro-nanoparticles is further studied. By using different ultrasonic loading degrees to realize Cu/Al soldering, it is believed that the understandings gained in this study may offer some new insights for the development of low-temperature soldering methodology for heterogeneous materials.
Yang, Haibo; Dai, Fengwei; Cao, Liqiang; Cao, Guofu; Fang, Zhidan; Wang, Qidong
2023 Microelectronics International
A large-scale detection system with more data in short time bins, small dead space and small signal identification is the ideology the scientists pursuing. These proposed demands are able to be solved by 2.5 D integration. The substance of a 2.5 D integration is called silicon interposer, which consists of the through silicon via (TSV) and redistribution layer. However, the state-of-the-art silicon interposer is not able to sustain its own mechanical strength with the detector/readout array often sitting as standalone in large science facilities and fails to reduce the expansions on the installation of the components due to its insufficient thickness and size. This study aims to propose a moderation of current interposer with large-sized, standalone properties.Design/methodology/approachThis paper proposes an interposer based on double-sided silicon vias (DSSVs) interconnection. Unlike conventional interposer that is interconnected by TSVs, DSSVs interposer is interconnected by top vias (T-vias) and bottom vias (B-vias).FindingsThe fabrication process of DSSVs interposer is introduced, and the superiority of the double-sided interconnection process with two etch-stop layers is described in detail. The impact of different T-vias depth on DSSVs interconnections in the same wafer is discussed and two times PI opening processes are proposed to eliminate air bubbles in the B-via. The relationship between the interposer thickness and warpage is studied by finite element analysis simulation and experiment. The prototype of the DSSVs interposer with a size of 100 × 100 mm and a thickness of 318.2 µm is fabricated, and electrical tests including short tests and continuity tests are carried out.Originality/valueThis paper proposes a large-sized and stand-alone interposer based on DSSVs interconnection.
Qi, Chunhua; Ma, Guoliang; Zhang, Yanqing; Wang, Tianqi; Rui, Erming; Jiao, Qiang; Liu, Chaoming; Huo, Mingxue; Zhai, Guofu
2023 Microelectronics International
The purpose of this paper is to present a transition detector (TD)-based radiation hardened flip-flop (TDRH-FF) for single event upset (SEU).Design/methodology/approachWith SEU recovery and single event transient (SET) detector mechanism, the TDRH-FF can tolerate SEU during hold mode and generate a warning signal for architecture-level recovery during transport mode when input signal contains SET. Evaluation results show that the TDRH-FF outperforms comparable comprehensive performance.FindingsSimulation results show that 1) the mean pulse width of the correction glitches (at full width half maximum) of TDRH-FF is less than 10 ps; 2) the area overhead of TDRH-FF is similar to the EVFERST-FF, BISER-FF and DNURHL-FF; 3) TDRH-FF has the same average power consumption as SETTOF, and moderate PDP and Ps values among these compared FFs.Originality/valueIn this paper, a TD-based TDRH-FF is proposed to solve the problems in the previous design. And the main contributions of the proposed TDRH-FF are summarized: Minimum size transistors are used in the proposed TD which leads to a considerable decrease in area overheads and propagation delay (resulting in an ignorable correction glitch); and compared with other radiation hardened flip-flop, TDRH-FF outperforms comparable comprehensive performance.
Xiao, Yuchen; Tang, Huiyi; Zhang, Hehe; Yang, Xiaoling; Sun, Ling; Xie, Yong; Wu, Baoan; Luan, Baifeng; Xie, Weidong; Cai, Xinnan
2023 Microelectronics International
The purpose of this paper is to develop high-performance Au-coated Ag alloy wires (ACAA wires) and demonstrate the effect of Au coating layers on the bonding performance and oxidation resistance for stable and reliable electronic packaging applications.Design/methodology/approachACAA wire with a diameter of approximately 25 µm and Au layer thickness of approximately 100 nm were prepared by the continuous casting, plating and wire drawing method. The bonding performance of the ACAA wires were studied through bonding on 3,535 chips. The oxidation resistance of ACAA wires and Ag alloy wires (AA wires) were comparatively studied by means of chemical oxidation tests, accelerated life tests and electrochemical tests systematically.FindingsACAA wires could form axi-symmetrical spherical free air balls with controllable diameter of 1.5∼2.5 times of the wire diameter after electric flame-off process. The ball shear strength of ACAA wire was higher than that of AA wires. Most importantly, because of the surface Au coating layer, the oxidation resistance of ACAA wires was much enhanced.Research limitations/implicationsACAA wires with different lengths of heat affected zone were not developed in this study, which limited their application with different loop height requirements.Practical implicationsWith higher bonding strength and oxidation resistance, ACAA wires would be a better choice than previous reported AA wire in chip packaging which require high stability and reliability.Originality/valueThis paper provides a kind of novel ACAA wire, which possess the merits of high bonding strength and reliability, and show great potential in electronic packaging applications.
Wang, Gang; Xia, Chenhui; Wang, Bo; Zhao, Xinran; Li, Yang; Yang, Ning
2023 Microelectronics International
A W-band antennas-in-packages (AIP) module with a hybrid stacked glass-compound wafer level fan-out process was presented. Heterogeneous radio frequency (RF) chips were integrated into one single module with a microscale fan-out process. This paper aims to find a new strategy for 5G communication with 3D integration of multi-function chips.Design/methodology/approachThe AIP module was composed of two stacked layers: the antenna layer and RF layer. After architecture design and performance simulation, the module was fabricated, The 8 × 8 antenna array was lithography patterned on the 12 inch glass wafer to reduce the parasitic parameters effect, and the signal feeding interface was fabricated on the backside of the glass substrate.FindingsAIP module demonstrates a size of 180 mm × 180mm × 1mm, and its function covers the complete RF front-end chain from the antenna to signal to process and can be applied in 5 G communication and automotive components.Originality/valueWith three RF multi-function chips and two through silicon via (TSV) chips were embedded in the 12 inch compound wafer through the fan-out packaging process; two layers were interconnected with TSV and re-distributed layers.
Zhang, Youxin; Liu, Yang; Cao, Rongxing; Zeng, Xianghua; Xue, Yuxiong
2023 Microelectronics International
Concerning the radiation effects on the three-dimensional (3D) packaging in space environment, this study aims to investigate the influence of the total dose effect on the transmission characteristics of high-frequency electrical signals using experimental and simulation methods.Design/methodology/approachThis work carries out the irradiation test of the specimens and measures their S21 parameters before and after irradiation. A simulation model describing the total dose effect was built based on the experimental test results. And, the radiation hardening design is evaluated by the simulation method.FindingsThe experimental results demonstrate that the S21 curve of the interconnection decreases with the increase of the irradiation dose, indicating that the total dose effect leads to the decline of its signal transmission characteristics. According to the simulation results, decreasing the height of the through silicon via (TSV), increasing the radius of the TSV, reducing the length of Si and increasing the number of grounded through silicon via have positive effects on improving the radiation resistance of the interconnection structure.Originality/valueThis work investigates the effect of radiation on the transmission characteristics of interconnection structures for 3D packaging and proposes the hardening design methods. It is meaningful for improving the reliability of 3D packaging in space applications.
Li, Ge; Kang, Qiushi; Niu, Fanfan; Wang, Chenxi
2023 Microelectronics International
Bumpless Cu/SiO2 hybrid bonding, which this paper aims to, is a key technology of three-dimensional (3D) high-density integration to promote the integrated circuits industry’s continuous development, which achieves the stacks of chips vertically connected via through-silicon via. Surface-activated bonding (SAB) and thermal-compression bonding (TCB) are used, but both have some shortcomings. The SAB method is overdemanding in the bonding environment, and the TCB method requires a high temperature to remove copper oxide from surfaces, which increases the thermal budget and grossly damages the fine-pitch device.Design/methodology/approachIn this review, methods to prevent and remove copper oxidation in the whole bonding process for a lower bonding temperature, such as wet treatment, plasma surface activation, nanotwinned copper and the metal passivation layer, are investigated.FindingsThe cooperative bonding method combining wet treatment and plasma activation shows outstanding technological superiority without the high cost and additional necessity of copper passivation in manufacture. Cu/SiO2 hybrid bonding has great potential to effectively enhance the integration density in future 3D packaging for artificial intelligence, the internet of things and other high-density chips.Originality/valueTo achieve heterogeneous bonding at a lower temperature, the SAB method, chemical treatment and the plasma-assisted bonding method (based on TCB) are used, and surface-enhanced measurements such as nanotwinned copper and the metal passivation layer are also applied to prevent surface copper oxide.
Li, Liyun; Zhang, Yu; Xia, Shiyu; Sun, Zhefei; Yuan, Junjie; Su, Dongchuan; Cao, Hunjun; Chai, Xiaoming; Wang, Qingtian; Li, Jintang; Zhang, Zhihao
2023 Microelectronics International
This study aims to develop a facile ligand-exchange strategy to promote nano-sintering of oleylamine (OAM)-capped silver nanoparticles (AgNPs). By using ligand exchange process with NH4OH to remove OAM from the surface of AgNP, this study reports effectively reducing the sintering temperature of AgNPs to achieve low-temperature nano-sintering. Compared with untreated AgNPs of OAM-capped, NH4OH-treated AgNPs possess superior sintering performance that could be applied to a fractional generator device as conductor and in favour of the fabrication of flexible circuit modules.Design/methodology/approachFirst, oleylamine is used as reductant to synthesize monodisperse AgNPs by a simple one-step method. Then ligand exchange is used with NH4OH at different treating times to remove OAM, and micro-Fourier transform infrared spectroscopy and contact angle test are applied to clear the mechanism and structure characteristics of these processes. Finally, NH4OH-treated AgNPs sediment sintering is used at different temperatures to test electrical resistivity and use ex situ scanning electron microscopy combined with in situ X-ray diffraction to study changes in microstructure in the whole nano-sintering process.FindingsThe AgNPs are always capped by organic ligands to prevent nanoparticles agglomeration. And oleylamine used as reductant could synthesize desirable size distributions of 8–32 nm with monodisperse globular shapes, but the low-temperature nano-sintering seemed not to be achieved by the oleylamine-capped AgNPs because OAM is an organic with long C-chain. The ligand exchange approach was enabled to replace the original organic ligands capped on AgNPs with organic ligands of low thermal stability which could promote nano-sintering. After ligand exchange treated AgNPs could be sintered on photo paper, polydimethylsiloxane (PDMS) and polyethylene terephthalate flexible substrates at low temperature.Originality/valueIn this research, the method ligand exchange is used to change the ligand of AgNPs. During ligand exchange, NH4OH was used to treat AgNPs. Through the treatment of NH4OH, the change of hydrophilic and hydrophobic properties of AgNPs was successfully realized. The sintering temperature of AgNPs can also be reduced and the properties can be improved. Finally, the applicability of the AgNPs sediment with this nano-sintering process at low temperature for obtaining conductive patterns was evaluated using PDMS as substrates.
Liu, Shaoyi; Yao, Songjie; Xue, Song; Wang, Benben; Jin, Hui; Pan, Chenghui; Zhang, Yinwei; Zhou, Yijiang; Zeng, Rui; Ping, Lihao; Min, Zhixian; Zhang, Daxing; Wang, Congsi
2023 Microelectronics International
Surface mount technology (SMT) is widely used and plays an important role in electronic equipment. The purpose of this paper is to reveal the effects of interface cracks on the fatigue life of SMT solder joint under service load and to provide some valuable reference information for improving service reliability of SMT packages.Design/methodology/approachA 3D geometric model of SMT package is established. The mechanical properties of SMT solder joint under thermal cycling load and random vibration load were solved by 3D finite element analysis. The fatigue life of SMT solder joint under different loads can be calculated by using the modified Coffin–Manson model and high-cycle fatigue model.FindingsThe results revealed that cracks at different locations and propagation directions have different effect on the fatigue life of the SMT solder joint. From the location of the cracks, Crack 1 has the most significant impact on the thermal fatigue life of the solder joint. Under the same thermal cycling conditions, its life has decreased by 46.98%, followed by Crack 2, Crack 4 and Crack 3. On the other hand, under the same random vibration load, Crack 4 has the most significant impact on the solder joint fatigue life, reducing its life by 81.39%, followed by Crack 1, Crack 3 and Crack 2. From the crack propagation direction, with the increase of crack depth, the thermal fatigue life of the SMT solder joint decreases sharply at first and then continues to decline almost linearly. The random vibration fatigue life of the solder joint decreases continuously with the increase of crack depth. From the crack depth of 0.01 mm to 0.05 mm, the random vibration fatigue life decreases by 86.75%. When the crack width increases, the thermal and random vibration fatigue life of the solder joint decreases almost linearly.Originality/valueThis paper investigates the effects of interface cracks on the fatigue life and provides useful information on the reliability of SMT packages.
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