Microelectronics International

Huang, Wenhua; Ren, Juan; Jiang, Jinglong; Cheng, J.

2021 Microelectronics International

doi: 10.1108/mi-01-2021-0006

Quantum-dot Cellular Automata (QCA) is a new nano-scale transistor-less computing model. To address the scaling limitations of complementary-metal-oxide-semiconductor technology, QCA seeks to produce general computation with better results in terms of size, switching speed, energy and fault-tolerant at the nano-scale. Currently, binary information is interpreted in this technology, relying on the distribution of the arrangement of electrons in chemical molecules. Using the coplanar topology in the design of a fault-tolerant digital comparator can improve the comparator’s performance. This paper aims to present the coplanar design of a fault-tolerant digital comparator based on the majority and inverter gate in the QCA.Design/methodology/approachAs the digital comparator is one of the essential digital circuits, in the present study, a new fault-tolerant architecture is proposed for a digital comparator based on QCA. The proposed coplanar design is realized using coplanar inverters and majority gates. The QCADesigner 2.0.3 simulator is used to simulate the suggested new fault-tolerant coplanar digital comparator.FindingsFour elements, including cell misalignment, cell missing, extra cell and cell dislocation, are evaluated and analyzed in QCADesigner 2.0.3. The outcomes of the study demonstrate that the logical function of the built circuit is accurate. In the presence of a single missed defect, this fault-tolerant digital comparator architecture will achieve 100% fault tolerance. Also, this comparator is above 90% fault-tolerant under single-cell displacement faults and is above 95% fault-tolerant under single-cell missing defects.Originality/valueA novel structure for the fault-tolerant digital comparator in the QCA technology was proposed used by coplanar majority and inverter. Also, the performance metrics and obtained results establish that the coplanar design can be used in the QCA circuits to produce optimized and fault-tolerant circuits.

Tahir, Muhammad Ahmad Raza; Saleem, Muhammad Mubasher; Bukhari, Syed Ali Raza; Hamza, Amir; Shakoor, Rana Iqtidar

2021 Microelectronics International

doi: 10.1108/mi-02-2021-0023

This paper aims to present an efficient design approach for the micro electromechanical systems (MEMS) accelerometers considering design parameters affecting the long-term reliability of these inertial sensors in comparison to traditional iterative microfabrication and experimental characterization approach.Design/methodology/approachA dual-axis capacitive MEMS accelerometer design is presented considering the microfabrication process constraints of the foundry process. The performance of the MEMS accelerometer is analyzed through finite element method– based simulations considering main design parameters affecting the long-term reliability. The effect of microfabrication process induced residual stress, operating pressure variations in the range of 10 mTorr to atmospheric pressure, thermal variations in the operating temperature range of −40°C to 100°C and impulsive input acceleration at different input frequency values is presented in detail.FindingsThe effect of residual stress is negligible on performance of the MEMS accelerometer due to efficient design of mechanical suspension beams. The effect of operating temperature and pressure variations is negligible on energy loss factor. The thermal strain at high temperature causes the sensing plates to deform out of plane. The input dynamic acceleration range is 34 g at room temperature, which decreases with operating temperature variations. At low frequency input acceleration, the input acts as a quasi-static load, whereas at high frequency, it acts as a dynamic load for the MEMS accelerometer.Originality/valueIn comparison with the traditional MEMS accelerometer design approaches, the proposed design approach focuses on the analysis of critical design parameters that affect the long-term reliability of MEMS accelerometer.

Kowalik, Piotr; Wróbel, Edyta

2021 Microelectronics International

doi: 10.1108/mi-04-2021-0032

This paper aims to present the possibility of computer-aided technology of chemical metallization for the production of electrodes and resistors based on Ni-P and Ni-Cu-P layers.Design/methodology/approachBased on the calculated parameters of the process, test structures were made on an alumina substrate using the selective metallization method. Dependences of the surface resistance on the metallization time were made. These dependencies take into account the comparison of the calculations with the performed experiment.FindingsThe author created a convenient and easy-to-use tool for calculating basic Ni-P and Ni-Cu-P layer parameters, namely, surface resistance and temperature coefficient of resistance (TCR) of test resistor, based on chemical metallization parameters. The values are calculated for a given level of surface resistance of Ni-P and Ni-Cu-P layer and defined required range of changes of TCR of test resistor. The calculations are possible for surface resistance values in the range of 0.4 Ohm/square ÷ 2.5 Ohm/square. As a result of the experiment, surface resistances were obtained that practically coincide with the calculations made with the use of the program created by the authors. The quality of the structures made is very good.Originality/valueTo the best of the authors’ knowledge, the paper presents a new, unpublished method of manufacturing electrodes (resistors) on silicon, Al2O3 and low temperature co-fired ceramic substrates based on the authors developed computer program.

Abdul Nasir, Nur Shahira; Deivasigamani, Revathy; Abdul Rahim, Muhammad Khairulanwar; Mohd Nashruddin, Siti Nur Ashakirin; Hamzah, Azrul Azlan; M. Razip Wee, M. Farhanulhakim; Buyong, Muhamad Ramdzan

2021 Microelectronics International

doi: 10.1108/mi-02-2021-0026

The purpose of this paper is to visualize protein manipulation using dielectrophoresis (DEP) as a substantial perspective on being an effective protein analysis and biosensor method as DEP is able to be used as a means for manipulation, fractionation, pre-concentration and separation. This research aims to quantify DEP using an electrochemical technique known as cyclic voltammetry (CV), as albumin is non-visible without any fluorescent probe or dye.Design/methodology/approachThe principles of DEP were generated by an electric field on tapered DEP microelectrodes. The principle of CV was analysed using different concentrations of albumin on a screen-printed carbon electrode. Using preliminary data from both DEP and CV methods as a future prospect for the integration of both techniques to do electrical quantification of DEP forces.FindingsThe size of the albumin is known to be 0.027 µm. Engineered polystyrene particle of size 0.05 µm was selected to mimic the DEP actuation of albumin. Positive DEP of the sample engineered polystyrene particle was able to be visualized clearly at 10 MHz supplied with 20 Vpp. However, negative DEP was not able to be visualized because of the limitation of the apparatus. However, albumin was not able to be visualized under the fluorescent microscope because of its translucent properties. Thus, a method of electrical quantification known as the CV technique is used. The detection of bovine serum albumin (BSA) using the CV method is successful. As the concentration of BSA increases, the peak current obtained from the voltammogram decreases. The peak current can be an indicator of DEP response as it correlates to the adsorption of the protein onto the electrodes. The importance of the results from both CV and DEP shows that the integration of both techniques is possible.Originality/valueThe integration of both methods could give rise to a new technique with precision to be implemented into the dialyzers used in renal haemodialysis treatment for manipulation and sensing of protein albumin.

Ishak, Mohammad Hafifi Hafiz; Abdul Aziz, Mohd Sharizal; Ismail, Farzad; Abdullah, M.Z.

2021 Microelectronics International

doi: 10.1108/mi-05-2021-0044

The purpose of this paper is to present the experimental and simulation studies on the influence of copper pillar bump structure on flip chip packaging during reflow soldering.Design/methodology/approachIn this work, solidification/melting modelling and volume of fluid modelling were used. Reflow soldering process of Cu pillar type FC was modelled using computational fluid dynamic software (FLUENT). The experimental results have been validated with the simulation results to prove the accuracy of the numerical method.FindingsThe findings of this study reveal that solder volume is the most important element influencing reflow soldering. The solder cap volume reduces as the Cu pillar bump diameter lowers, making the reflow process more difficult to establish a good solder union, as less solder is allowed to flow. Last but not least, the solder cap height for the reflow process must be optimized to enable proper solder joint formation.Practical implicationsThis study provides a basis and insights into the impact of copper pillar bump structure on flip chip packaging during reflow soldering that will be advancing the future design of 3D stack package. This study also provides a superior visualization and knowledge of the melting and solidification phenomenon during the reflow soldering process.Originality/valueThe computational fluid dynamics analysis of copper pillar bump structure on flip chip packaging during reflow soldering is scant. To the authors’ best knowledge, no research has been concentrated on copper pillar bump size configurations in a thorough manner. Without the in-depth study, copper pillar bump size might have the impact of copper pillar bump structure on flip chip packaging during reflow soldering. Five design of parameter of flip chip IC package model was proposed for the investigation of copper pillar bump structure on flip chip packaging during reflow soldering.

Lim, Chong Hooi; Abdullah, Mohd Zulkifly; Abdul Aziz, Ishak; Khor, Chu Yee; Abdul Aziz, Mohd Sharizal

2021 Microelectronics International

doi: 10.1108/mi-06-2021-0049

This study aims to investigate the interaction of independent variables [Reynolds number (Re), thermal power and the number of ball grid array (BGA) packages] and the relation of the variables with the responses [Nusselt number ((Nu) ¯ ), deflection/FPCB’s length (d/L) and von Mises stress]. The airflow and thermal effects were considered for optimizing the Re of various numbers of BGA packages with thermal power attached on flexible printed circuit board (FPCB) for optimum cooling performance with least deflection and stress by using the response surface method (RSM).Design/methodology/approachFlow and thermal effects on FPCB with heat source generated in the BGA packages have been examined in the simulation. The interactive relationship between factors (i.e. Re, thermal power and number of BGA packages) and responses (i.e. deflection over FPCB length ratio, stress and average Nusselt number) were analysed using analysis of variance. RSM was used to optimize the Re for the different number of BGA packages attached to the FPCB.FindingsIt is important to understand the behaviour of FPCB when exposed to both flow and thermal effects simultaneously under the operating conditions. Maximum d/L and von Misses stress were significantly affected by all parametric factors whilst (Nu)¯ is significantly affected by Re and thermal power. Optimized Re for 1–3 BGA packages with maximum thermal power applied has been identified as 21,364, 23,858 and 29,367, respectively.Practical implicationsThis analysis offers a better interpretation of the parameter control in FPCB with optimized Re for the use of force convection electronic cooling. Optimal Re could be used as a reference in the thermal management aspect in designing the BGA package.Originality/valueThis research presents the parameters’ effects on the reliability and heat transfer in FPCB design. It also presents a method to optimize Re for the different number of BGA packages attached to increase the reliability in FPCB’s design.

Plascencia Jauregui, Francisco Javier; Medina Vazquez, Agustín Santiago; Becerra Alvarez, Edwin Christian; Arce Zavala, José Manuel; Flores Ruiz, Sandra Fabiola

2021 Microelectronics International

doi: 10.1108/mi-01-2021-0004

This study aims to present a mathematical method based on Poisson’s equation to calculate the voltage and volume charge density formed in the substrate under the floating gate area of a multiple-input floating-gate metal-oxide semiconductor metal-oxide semiconductor (MOS) transistor.Design/methodology/approachBased on this method, the authors calculate electric fields and electric potentials from the charges generated when voltages are applied to the control gates (CG). This technique allows us to consider cases when the floating gate has any trapped charge generated during the manufacturing process. Moreover, the authors introduce a mathematical function to describe the potential behavior through the substrate. From the resultant electric field, the authors compute the volume charge density at different depths.FindingsThe authors generate some three-dimensional graphics to show the volume charge density behavior, which allows us to predict regions in which the volume charge density tends to increase. This will be determined by the voltages on terminals, which reveal the relationship between CG and volume charge density and will allow us to analyze some superior-order phenomena.Originality/valueThe procedure presented here and based on coordinates has not been reported before, and it is an aid to generate a model of the device and to build simulation tools in an analog design environment.