Microelectronics International

Guangbin Tan; Ping Yang; Tianbo Li; Tao Xi; Xiaoming Yuan; Jianming Yang

2012 Microelectronics International

doi: 10.1108/13565361211237653

Purpose – The purpose of this paper is to provide a systematic method to perform analysis and test for vibration‐thermal strain behavior of plastic ball grid array (PBGA) assembly by considering thermal and vibration loading mode. Also to investigate the dynamic behavior of PBGA assembly by considering loading modes for design and reliability evaluation of PBGA packaging. Design/methodology/approach – A PBGA assembly prototype with different structure and material parameters is designed and manufactured. Based on investigation of the structural and physical parameters of PBGA sample, the vibration‐thermal strain test is developed to measure the strain distribution at the surface of the BT (bismaleimide triazine) substrates and PCB (printed circuit board) surface under vibration‐thermal cycling loading such as random vibration and the temperature is changed from 0°C to 100°C. Findings – The test results show that the loading modes have different impact on PCB, EMC and substrate, respectively. In the meantime, it is shown that the characteristics of the compound mode is not the linear accumulative result by single vibration mode and single thermal loading mode as forecasted. The nonlinear mechanism for these modes application is the future work for progress. Research limitations/implications – It is very difficult to set up a numerical approach to illustrate the validity of the testing approach because the complex loading modes and the complex structure of PBGA assembly. The research on an accurate mathematical model of the PBGA assembly prototype is a future work. Practical implications – It implies a potential design characteristic for future application of PBGA assembly. It also builds a basis for future work for design and reliability evaluation of BGA package. Originality/value – This paper fulfils useful information about the thermal‐vibration coupling dynamic behavior of PBGA assembly with different structure characteristics, materials parameters.

Kah‐Yoong Chan; Hee‐Joe Phoon; Chee‐Pun Ooi; Wai‐Leong Pang; Sew‐Kin Wong

2012 Microelectronics International

doi: 10.1108/13565361211237662

Purpose – Power management of a wireless sensor node is important and needs to be designed efficiently without wasting excessive energy. The purpose of this paper is to report on the improvement of the power management of a wireless sensor node. Design/methodology/approach – The design involves the implementation of solar recharging technology with single‐ended primary inductance converter (SEPIC) on a wireless sensor node in order to achieve the improvement in power management. Findings – The combination of the solar recharging technology with SEPIC converter shows promising results for efficiently supplying the power to the wireless sensor node. Research limitations/implications – The design idea can be extended for many other electronic sensor applications, which can help to ensure an efficient power management of the sensor nodes. Originality/value – The proposed design model demonstrates a new idea towards reduction of energy usage for wireless sensor nodes.

Mirjana S. Damnjanović; Ljiljana D. Živanov; Snezana M. Djurić; Andrea M. Marić; Aleksandar B. Menićanin; Goran J. Radosavljević; Nelu V. Blaž

2012 Microelectronics International

doi: 10.1108/13565361211237671

Purpose – Significant achievements in ferrite material processing enable developments of many ferrite devices with a wide range of power levels and working frequencies, which make demands for new characterization and modelling methods for ferrite materials and components. The purpose of this paper is to introduce a modelling and measurement procedure, which can be used for the characterization of two‐port ferrite components in high frequency range. Design/methodology/approach – This paper presents a commercially available ferrite component (transformer) modelling and determination of its electrical parameters using in‐house developed software. The components are measured and characterized using a vector network analyzer E5071B and adaptation test fixture on PCB board. The parameters of electrical equivalent circuit of the ferrite transformer parameters are compared with values extracted out of measured scattering parameters. Findings – A good agreement between modelled and extracted electrical parameters of the ferrite transformer is found. The modelled inductance curves have the same dependence versus frequency as extracted ones. That confirms the model validity in the wide frequency range. Originality/value – In‐house developed software based on proposed model provides inclusion of the ferrite material dispersive characteristics, which dominantly determines high‐frequency behaviour of two‐port ferrite components. Developed software enables fast and accurate calculation of the ferrite transformer electrical parameters and its redesign in order to achieve the best performance for required application.

Mei‐Ling Yeh; Yao‐Chian Lin; Wei‐Chieh Chang

2012 Microelectronics International

doi: 10.1108/13565361211237680

Purpose – The purpose of this paper is to design a low phase noise and high figure of merit, fully integrated, voltage‐controlled oscillator (VCO) which was fabricated in TSMC CMOS 0.18‐μm 1P6M process. Design/methodology/approach – A differential PMOS cross‐coupled architecture VCO with the capacitive feedback technology was designed to increase the linearity of frequency tuning range and decrease the phase noise. Varactor determining the performance of tuning range is also a key component in the design of VCO. The authors adopt the accumulation‐mode MOS varactor. The output spectrum and the phase noise are measured by E5052A spectrum analyzer. Findings – The VCO is successfully fabricated in TSMC RF CMOS 0.18um 1P6M process. The measured tuning range is from 10.875 GHz ∼ 11.1 GHz with control voltage from 0 to 1.5 V. The measured phase noise is as low as −120.42 dBc/Hz at 1 MHz offset and the high FOM is −189.5 dBc/Hz. The output spectrum is −10.51dBm with center oscillator frequency of 10.942 GHz. The core circuit without buffer consumes power of 15 mW from a 1.8 V supply voltage. Originality/value – This paper shows a fully integrated CMOS LCVCO architecture using capacitive feedback technology with low phase noise and high figure of merit for OC‐192 SONET applications.

Ang Chai Im; Leonard Lu Tze Jian; Ooi Poh Kok; Suriani Yaakob; Ching Chin Guan; Ng Sha Shiong; Zainuriah Hassan; Haslan Abu Hassan; Mat Johar Abdullah

2012 Microelectronics International

doi: 10.1108/13565361211237699

Purpose – The purpose of this paper is to synthesize porous zinc oxide (ZnO) by means of strain etching/wet chemical etching method with the use of 0.5% of nitric acid (HNO 3 ) etchant. The structural and surface morphological properties of the samples are accessed by using X‐ray diffraction (XRD) and scanning electron microscopy (SEM) characterization techniques. Design/methodology/approach – ZnO samples used in this work were deposited on the p‐Si (111) substrates by using radio frequency (RF) sputtering technique. Wet chemical etching processes with the use of 0.5% HNO 3 etchant was applied on these samples in order to obtain porous structure. The porous ZnO samples are characterized by means of XRD and SEM to access their structural and surface morphological properties. Findings – The XRD and SEM cross‐sectional measurements revealed that the thickness of the etched ZnO thin films is proportional to the etching time. SEM micrographs show that the surface morphology of ZnO changes over etching time. On the other hand, XRD results indicate that the crystallite sizes of the ZnO(002) decreases when the etching time increases. Originality/value – The paper shows how porous ZnO thin films have been successfully synthesized by using simple wet chemical etching. SEM images reveal that this method is reliable when producing porous structure ZnO surfaces.

Bouraoui Ouni; Abdellatif Mtibaa

2012 Microelectronics International

doi: 10.1108/13565361211237707

Purpose – The purpose of this paper is to reduce the reconfiguration time of a field‐programmable gate array (FPGA). Design/methodology/approach – The paper focuses on introducing a new temporal placement algorithm which uses a typical mathematical formalism to optimize the reconfiguration time. Findings – Results show that the algorithm decreases considerably the reconfiguration time compared with famous temporal placement algorithms. Originality/value – The paper proposes a new temporal placement algorithm which optimizes reconfiguration time of modules on the device. The studied evaluation cases show that the proposed algorithm provides very significant results in terms reconfiguration time of modules versus other well‐known algorithms used in the temporal placement field. The authors uses the eigenvalue of the Laplacian matrix.

Dhafer Abdul‐Ameer Shnawah; Mohd Faizul Mohd Sabri; Irfan Anjum Badruddin; Fa Xing Che

2012 Microelectronics International

doi: 10.1108/13565361211237716

Purpose – The purpose of this paper is to investigate the effect of Al addition on the bulk alloy microstructure and tensile properties of the low Ag‐content Sn‐1Ag‐0.5Cu (SAC105) solder alloy. Design/methodology/approach – The Sn‐1Ag‐0.5Cu‐ x Al ( x =0, 1, 1.5 and 2 wt.%) bulk solder specimens with flat dog‐bone shape were used for tensile testing in this work. The specimens were prepared by melting purity ingots of Sn, Ag, Cu and Al in an induction furnace. Subsequently, the molten alloys were poured into pre‐heated stainless steel molds, and the molds were naturally air‐cooled to room temperature. Finally, the molds were disassembled, and the dog‐bone samples were removed. The solder specimens were subjected to tensile testing on an INSTRON tester with loading rate 10 −3 s −1 . The microstructural analysis was carried out using scanning electron microscopy/Energy dispersive X‐ray spectroscopy. Electron Backscatter Diffraction (EBSD) analysis was used to identify the IMC phases. To obtain the microstructure, the solder samples were prepared by dicing, molding, grinding and polishing processes. Findings – The addition of Al to the SAC105 solder alloy suppresses the formation of Ag 3 Sn and Cu 6 Sn 5 IMC particles and leads to the formation of larger Al‐rich and Al‐Cu IMC particles and a large amount of fine Al‐Ag IMC particles. The addition of Al also leads to refining of the primary β‐Sn grains. The addition of Al results in a significant increase on the elastic modulus and yield strength. On the other hand, the addition of Al drastically deteriorates the total elongation. Originality/value – The addition of Al to the low Ag‐content SAC105 solder alloy has been discussed for the first time. This work provides a starting‐point to study the effect of Al addition on the drop impact and thermal cycling reliability of the SAC105 alloy.