Microelectronics International

V.T.S. Dao; T.G. Etoh; M. Tanaka; T. Akino

2009 Microelectronics International

doi: 10.1108/13565360910981508

Purpose – The purpose of this paper is to minimize on‐chip inductance effect for modern very large‐scale integration (VLSI), ultra large‐scale integration (ULSI) systems. Design/methodology/approach – As operating frequency increases, parasitic inductance has become a major concern for electronic design on both delay and coupling noises. The impacts of on‐chip inductance are strongly associated with higher frequency operation, denser interconnect geometry, reductions of resistance, and capacitance of interconnects. The paper presents a novel layout technique – opposing inter‐digitating routing, to generate magnetic fields in opposing directions; consequently, effective magnetic field is minimized, or inductance effect is reduced. To prove the effectiveness of these approaches, 3D field solver FastHenry is used to extract inductance data and verify the results. Findings – Verification shows that this proposed method gives more than ten times reduction in self‐inductance while mutual inductance reduces even faster, without incurring any area and resource penalty. Originality/value – The proposed technique can be used effectively to minimize inductance effects in the design of modern interconnect structures. This technique is shown to be highly effective for inductance reduction in wide signal buses which are used frequently in global buses, critical data path or clock distribution networks of VLSI and ULSI systems.

J. Buckley; B. O'Flynn; J. Barton; S.C. O'Mathuna

2009 Microelectronics International

doi: 10.1108/13565360910981517

Purpose – The purpose of this paper is to develop a highly miniaturized wireless inertial sensor system based on a novel 3D packaging technique using a flexible printed circuit (FPC). The device is very suitable for wearable applications in which small size and lightweight are required such as body area network, medical, sports and entertainment applications. Design/methodology/approach – Modern wireless inertial measurement units are typically implemented on a rigid 2D printed circuit board (PCB). The design concept presented here is based around the use of a novel planar, six‐faceted, crucifix or cross‐shaped FPC instead of a rigid PCB. A number of specific functional blocks (such as microelectromechanical systems gyroscope and accelerometer sensors, microcontroller (MCU), radio transceiver, antenna, etc.) are first assigned to each of the six faces which are each 1 cm 2 in area. The FPC cross is then developed into a 1 cm 3 , 3D configuration by folding the cross at each of five bend planes. The result is a low‐volume and lightweight, 1 cm 3 wireless inertial sensor that can sense and send motion sensed data wirelessly to a base station. The wireless sensor device has been designed for low power operation both at the hardware and software levels. At the base station side, a radio receiver is connected to another MCU unit, which sends received data to a personal computer (PC) and graphical user interface. The industrial, scientific and medical band (2.45 GHz) is used to achieve half duplex communication between the two sides. Findings – A complete wireless sensor system has been realized in a 3D cube form factor using an FPC. The packaging technique employed during the work is shown to be efficient in fabricating the final cubic system and resulted in a significant saving in the final size and weight of the system. A number of design issues are identified regarding the use of FPC for implementing the 3D structure and the chosen solutions are shown to be successful in dealing with these issues. Research limitations/implications – Currently, a limitation of the system is the need for an external battery to power the sensor system. A second phase of development would be required to investigate the possibility of the integration of a battery and charging system within the cube structure. In addition, the use of flexible substrate imposes a number of restrictions in terms of the ease of manufacturability of the final system due to the requirement of the required folding step. Practical implications – The small size and weight of the developed system is found to be extremely useful in different deployments. It would be useful to further explore the system performance in different application scenarios such as wearable motion tracking applications. In terms of manufacturability, component placement needs to be carefully considered, ensuring that there is sufficient distance between the components, bend planes and board edges and this leads to a slightly reduced usable area on the printed circuit. Originality/value – This paper provides a novel and useful method for realizing a wireless inertial sensor system in a 3D package. The value of the chosen approach is that a significant reduction in the required system volume is achieved. In particular, a 78.5 per cent saving in volume is obtained in decreasing the module size from a 25 to a 15 mm 3 size.

Yusuf Onur Koçberber; Yusuf Osmanlıoğlu; Oğuz Ergin

2009 Microelectronics International

doi: 10.1108/13565360910981526

Purpose – The purpose of this paper is to reduce parity generation latency if the input value is narrow. Design/methodology/approach – Soft errors caused by cosmic particles and radiation emitted by the packaging are important problems in contemporary microprocessors. Parity bits are used to detect single bit errors that occur in the storage components. In order to implement parity logic, multiple levels of XOR gates are used and these XOR trees are known to have high delay. Many produced and consumed values inside a processor hold consecutive zeros and ones in their upper order bits. These values can be represented with less number of bits and hence are termed narrow. In this paper, a parity generator circuit design is proposed that is capable of generating parity if the input value is narrow. It is shown that the parity can be generated faster than a regular XOR tree implementation using this design for the values that can be represented using fewer bits. Findings – The proposed technique reduces the parity generation latency of 64‐bit values by 50 percent for eight‐bit narrow values. Considering the fact that around 70 percent of the immediate values written to the immediate field of the issue queue and around 40 percent of the value written to the integer register file can be expressed with only eight bits, the coverage of the proposed scheme is quite high. Originality/value – This paper shows the simulation results of fast parity generator circuit if the input value is narrow.

O.S. Aleksic; S.M. Savic; M.V. Nikolic; L. Sibinoski; M.D. Lukovic

2009 Microelectronics International

doi: 10.1108/13565360910981535

Purpose – The purpose of this paper is to apply negative thermal coefficient (NTC) thick film segmented thermistors (TFSTs) in a micro‐flow sensor for water. Design/methodology/approach – A TFST is printed using NTC paste based on nickel manganite. The resistance of this thermistor is measured in a climatic chamber and the resulting curves are calibrated. A micro‐flow sensor is designed using a self‐heated segmented thermistor. The sensing principle is based on heat loss depending on the water flow intensity through the capillary. Water flow calibration is performed. The sensor sensitivity, inertia, and stability are analyzed. Findings – The micro‐flow sensor exhibits good stability, suitable sensitivity, and inertia for integral measurements of water flow. Practical implications – Advantages of a micro‐flow sensor using a TFST include low energy consumption, simple measuring procedure, and passive electronics. Originality/value – This paper describes initial work on a micro‐flow sensor for water using TFSTs.

Zhi‐Yuan Cui; Joong‐Ho Choi; Yeong‐Seuk Kim; Shi‐Ho Kim; Nam‐Soo Kim

2009 Microelectronics International

doi: 10.1108/13565360910981544

Purpose – The purpose of this paper is to describe the application of low‐glitch current cell in a digital to analog converter (DAC) to reduce the clock‐feedthrough effect and achieve a low power consumption. Design/methodology/approach – A low‐glitch current switch cell is applied in a ten‐bit two‐stage DAC which is composed of a unary cell matrix for six most significant bits and a binary weighted array for four least significant bits (LSBs). The current cell is composed of four transistors to neutralize the clock‐feedthrough effect and it enables DAC to operate in good linearity and low power consumption. The prototype DAC is being implemented in a 0.35μm complementary metal‐oxide semiconductor process. The reduction in glitch energy and power consumption has been realized by preliminary experiment and simulation. Findings – Compared to conventional current cell, more than 15 per cent reduction of glitch energy has been obtained in this work. The DAC is estimated that differential nonlinearity is within 0.1 LSB and the maximum power consumption is 68 mW at the sampling frequency of 100 MHz. Originality/value – Comparison with other conventional work indicates that the current cell proposed in this paper shows much better performance in terms of switching spike and glitch, which may come from the extra dummy transistor in cell and reduce the clock‐feedthrough effect.

Chien‐Yi Huang; Ming‐Shu Li; Chen‐Liang Ku; Hao‐Chun Hsieh; Kung‐Cheng Li

2009 Microelectronics International

doi: 10.1108/13565360910981553

Purpose – The purpose of this paper is to discuss the chemical characterization of failures and process materials for microelectronics assembly. Design/methodology/approach – The analytical techniques used for chemical structures and compositions including Fourier transform infrared spectrometer (FTIR), scanning electron microscopy, and energy‐dispersive X‐ray spectroscopy are conducted. Findings – The residues on the golden finger are identified to be the flux used in the assembly processes. Besides, the contaminants on the processed and incoming connector pins are verified to be polyamides (–CONH functional groups) from housing material's residue. Three liquid fluxes used in wave soldering are analyzed by their chemical structure. One flux showing the OH groups at 3430 cm −1 indicates higher acid contents. This consists with the acidic values specified by the supplier. Also, the solder mask under study has ever appeared peeled‐off issue. The FTIR spectra results indicated 62.2 percent degree of curing while vendor's spec is above 70 percent. Originality/value – The establishment of the Infrared spectra database for fluxes and process materials help determine the root cause of the contaminants to reduce re‐occurrence of similar problems and thus enhance the manufacturing capability. The infrared spectrophotometry technique can be used by professional original design manufacturing and/or electronics manufacturing service, providers to investigate board/component defects during product pilot run stage and volume production.

K.G. Verma; B.K. Kaushik; R. Singh

2009 Microelectronics International

doi: 10.1108/13565360910981562

Purpose – Process variation has become a major concern in the design of many nanometer circuits, including interconnect pipelines. The purpose of this paper is to provide a comprehensive overview of types and sources of all aspects of interconnect process variations. Design/methodology/approach – The impacts of these interconnect process variations on circuit delay and cross‐talk noises along with the two major sources of delays – parametric delay variations and global interconnect delays – have been discussed. Findings – Parametric delay evaluation under process variation method avoids multiple parasitic extractions and multiple delay evaluations as is done in the traditional response surface method. This results in significant speedup. Furthermore, both systematic and random process variations have been contemplated. The systematic variations need to be experimentally modeled and calibrated while the random variations are inherent fluctuations in process parameters due to any reason in manufacturing and hence are non‐deterministic. Originality/value – This paper usefully reviews process variation effects on very large‐scale integration (VLSI) interconnect.

Vaishali Mane; Vijaya Puri

2009 Microelectronics International

doi: 10.1108/13565360910981571

Purpose – The purpose of this paper is to report on the Ku band microwave characteristics of moisture laden soya seeds using overlay technique. Design/methodology/approach – Ku band (13‐18 GHz) moisture dependent microwave permittivity, conductivity, penetration depth of moisture laden soybean (Glycine Max) using overlay on Ag thick film equilateral triangular patch antenna are studied. The change in the frequency response of the patch antenna due to change in moisture content of the soybean overlay has been used to obtain the various microwave properties. Findings – The permittivities obtained are in the range expected of moisture laden soybean. As moisture content increases microwave dielectric constant, dielectric loss, and conductivity of soybean increases. Only the amplitude data have been used here. Originality/value – Ku band characterization of soybean has been done using overlay technique. The thick film patch antenna is sensitive even to ∼4 percent moisture content in the overlay material. This can be used for even moisture sensing at low moisture levels. This paper is believed to be an original research report.