Microelectronics International

Yung‐Hsiang Hung

2007 Microelectronics International

doi: 10.1108/13565360710779136

Purpose – The aim of this research is to combine the Taguchi method and hybrid methods of artificial intelligence, to use them as the optimal tool in wire bond designing parameters for an ultra‐thin chip scale package (CSP) package, and then construct a set of the optimal parameter analysis flow and steps. Design/methodology/approach – The hybrid methodology of artificial Intelligence was used in order to identify the optimum parameters design for a wire bonding of ultra‐thin CSP package. This paper employed desirability function to integrate two quality characteristics (loop height and wire pull strength) into a single quality indicator to construct a well‐trained neural network prediction system with hybrid genetic algorithm. Findings – The processes parameters of low‐loop of micro HDD driver IC were optimized with GA, thereby achieving the objective of improving process yield and robustness design of micro HDD driver IC. Practical implications – The engineers could quickly obtain the optimal production process parameter with the demand of multi‐quality characteristics, and enhance the assembly quality and yield of driver IC of micro HDD. Originality/value – This paper applies the design of experiments approach to a lower wire loop processes parameters design, and improves the process yield and robustness design of micro HDD driver IC.

Min Tang; J.F. Mao; L.L. Jiang

2007 Microelectronics International

doi: 10.1108/13565360710779145

Purpose – This paper aims to obtain the optimal wire sizing of buffered global interconnects and to investigate the impact of weight factor on the optimized system performance for various technology nodes. Design/methodology/approach – The width and spacing of interconnects are optimized under two scenarios, and corresponding optimum line width is determined by minimizing the value of power‐delay product which is defined as a figure of merit (FOM). Based on the results, the impact of weight factor on the optimized system performance, such as delay and power dissipation per unit length, is analyzed for various technology nodes. Findings – The analytical expressions of the optimum width are derived under two scenarios. Better FOMs can be achieved for the S = W scenario, but the wireability of the chip degrades considerably. The optimized delay increases with the increasing of weight factor, while the optimized power dissipation decreases with it. For a given weight factor, smaller latency and less power dissipation can be achieved for the S = W case. Originality/value – The analytical expressions of the optimum width of interconnects are given, and a comprehensive study of the impact of weight factor on the optimized results under two scenarios is presented.

Z.W. Zhong; T.Y. Tee; J‐E. Luan

2007 Microelectronics International

doi: 10.1108/13565360710779154

Purpose – This paper seeks to review recent advances in wire bonding, flip chip and lead‐free solder for advanced microelectronics packaging. Design/methodology/approach – Of the 91 journal papers, 59 were published in 2005‐2007 and topics related to wire bonding, flip chip and lead‐free solder for advanced microelectronics packaging are reviewed. Findings – Research on advanced wire bonding is continuously performed for advanced and complex applications such as stacked‐dies wire bonding, wire bonding of low‐ k ultra‐fine‐pitch devices, and copper wire bonding. Owing to its many advantages, flip chip using adhesive has gained more popularity. Research on the reliability of lead‐free solder joints is being conducted world‐wide. The new challenges, solutions and new developments are discussed in this paper. Research limitations/implications – Because of page limitation of this review paper and the large number of the journal papers available, only a brief review is conducted. Further reading is needed for more details. Originality/value – This review paper attempts to provide introduction to recent developments and the trends in terms of the topics for advanced microelectronics packaging. With the references provided, readers may explore more deeply, focusing on a particular issue.

Winco K.C. Yung; Jijun Zhu

2007 Microelectronics International

doi: 10.1108/13565360710779163

Purpose – Low temperature co‐fired ceramics (LTCC) material is introduced as an excellent alternative to silicon, glass, or plastic materials for the fabrication of miniaturised analytical devices, though it is most widely used in the automotive and microwave industries. The paper aims to study the laser ablation of LTCC material. Design/methodology/approach – This kind of green tape material is mechanised by excimer laser (KrF, 248 nm) and UV laser (Nd: YAG, 355 nm), and for the first time by infra‐red laser (1,090 nm). The optical photos and the scanning electronic microscope (SEM) photos of the LTCC ablated by different kinds of laser sources are given in this paper. Findings – When using the UV laser, the tapered structure can be easily seen from the SEM photo. However, a kind of clear and perfect ablation of LTCC can be seen for the first time by the 1,090 nm infra‐red laser ablation. Originality/value – The laser ablation of LTCC by optical fibre sources is discussed.

Harikrishnan Ramiah; Tun Zainal Azni Zulkifli

2007 Microelectronics International

doi: 10.1108/13565360710779172

Purpose – This paper sets out to design and realize a highly linear, wide dynamic range and high switching efficiency integrated CMOS up‐conversion mixer for two‐step IEEE 802.1a WLAN transmitter application in 0.18‐ μ m deep submicron CMOS technology. Design/methodology/approach – A folded current draining low‐voltage mixer architecture is explored and an extensive simulation carried out utilizing Cadence Spectre‐RF tool in optimizing the linearity, input third‐order intercept point (IIP3), the dynamic range, 1 dB compression point (P −1dB ), power dissipation and reduction of switching quad C gs , input gate‐source capacitance, in enhancing the switching efficiency of the proposed architecture. Findings – A highly linear, high input dynamic range, low voltage folded up‐conversion mixer architecture is realized in a significant comparable performance with respect to conventional reported architecture, indicating −8.87 dBm of OIP3 corresponding to 15.27 dBm IIP3 and 4.37 dBm of P −1dB in 0.18‐μm CMOS technology. Research limitations/implications – The optimized mixer architecture is stringent to an up‐converter application. To be utilized as a down converter at the receiver end, parameters, namely as noise figure and conversion gain, are of additional importance. Practical implications – The designed folded mixer architecture is in need of integration to a two‐step up‐conversion transmitter architecture which relaxes the injection pulling effect for a given low voltage headroom, with low power dissipation design. Originality/value – In this work, an integrated folded architecture with on‐chip process, voltage and temperature compensated biasing circuit is explored and enhanced, raising awareness of adapting improved multiplier blocks in achieving optimal performance in WLAN transceiver architecture.

Brajesh Kumar Kaushik; Sankar Sarkar; R.P. Agarwal; R.C. Joshi

2007 Microelectronics International

doi: 10.1108/13565360710779181

Purpose – This paper proposes to study the effect of line resistance and driver width on crosstalk noise for a CMOS gate driven inductively and capacitively coupled VLSI interconnects. Design/methodology/approach – The paper considers a distributed RLC interconnect topology. The interconnect length is 4 mm and far‐end capacitive loading is 30 fF. The SPICE simulation set‐up uses an IBM 0.13 μ m, 1.2 V technology model. The input falling ramp has a transition time of 50 ps. The victim line is grounded through a driver resistance of 50 Ω at near end of interconnect. While observing the effect of line resistance, the aggressor driver has PMOS and NMOS widths of 70 and 30 μ m, respectively, and the line resistance is varied from 0 to 500 Ω. For capturing the effect of driver width, SPICE waveforms are generated at far end of victim line for three different line resistances ( R =0, 30, and 60 Ω respectively). In each case, the aggressor PMOS driver width is swept from 20 to 100 μ m. The corresponding NMOS width is half of PMOS width. Findings – It is observed that, as line resistance increases, the noise peak reduces. This is due to the fact that with increasing resistance the incident and reflected waves traveling along the line experience increasing attenuation. Hence, the waves arriving at the far‐end of the line are of smaller magnitude and larger time durations. This causes noise pulses in the lossy lines to be smaller and wider compared with those in a lossless line. The effect of driver width on noise waveforms is further observed. It is observed that, as the PMOS (and corresponding NMOS) driver width is increased, the victim line gets more prone to crosstalk noise. The crosstalk magnitude level increases alarmingly as driver width is increased, because the driver resistance decreases, which in turn increases the current driving capability of driver. Originality/value – While designing coupled interconnects, driver width and line resistance play an important role in deciding the crosstalk level. An interconnect designer often increases driver width and reduces line resistance for achieving lower propagation delays. This effort may result in higher crosstalk noise in coupled interconnect. Therefore, a designer should be concerned simultaneously for crosstalk noise while reducing delays.

Kaiçar Ammous; Slim Abid; Anis Ammous

2007 Microelectronics International

doi: 10.1108/13565360710779190

Purpose – The paper aims to focus on the semiconductor temperature prediction in the multichip modules by using a simplified 1D model, easy to implement in the electronic simulation tools. Design/methodology/approach – Accurate prediction of temperature variation of power semiconductor devices in power electronic circuits is important for obtaining optimum designs and estimating reliability levels. Temperature estimation of power electronic devices has generally been performed using transient thermal equivalent circuits. This paper has studied the thermal behaviour of the power modules. The study leads to correcting the junction temperature values estimated from the transient thermal impedance of each component operating alone. The corrections depend on multidimensional thermal phenomena in the structure. Findings – The classic analysis of thermal phenomena in the multichip structures, independently of powers’ dissipated magnitude and boundary conditions, is not correct. An advanced 1D thermal model based on the finite element method is proposed. It takes into account the effect of the heat‐spreading angle of the different devices in the module. Originality/value – The paper focuses on mathematical model of the thermal behaviour in the power module. The study leads to a correction of the junction temperature values estimated from the transient thermal impedance of each component given by manufacturers. The proposed model gives a good trade‐off between accuracy, efficiency and simulation cost.

U.B. Lonkar; Vijaya Puri

2007 Microelectronics International

doi: 10.1108/13565360710779208

Purpose – This paper aims to study tuning effects on thick film microstripline due to ferrite thick film overlay. Design/methodology/approach – The possibility of obtaining tuning characteristics in the Ku band microwave region in the absence of external magnetic field by a simple process of using Ni x Zn 1− x Fe 2 O 4 thick film and bulk as in‐touch overlay over Ag thick film microstripline was investigated. The microstripline is basically a non‐resonant component with high‐transmission at a large microwave frequency band. The ferrite was synthesized by precursor method and the thick films were deposited by screen printing. Findings – It was found that tuning characteristics were observed and composition, thickness and precursor dependent changes occurred. The changes with composition are more prominent in the 14.5‐16.5 GHz range. Also, the ferrite thick film overlay produces a deep notch at 15.7 GHz. It is observed that the pellet overlay also makes the microstripline very dispersive with a high‐insertion loss in the 16‐17 GHz range. The presence of permeability‐related effects interfering with the normal propagation of the microstrip circuits might be causing the changes in the circuits. Originality/value – Owing to the Ni x Zn 1− x Fe 2 O 4 overlay the simple microstripline can be tuned to have narrow band filter type of characteristics. Thick film Ni x Zn 1− x Fe 2 O 4 overlay gives the added advantage of planer configuration along with cost‐effectiveness in the absence of magnetic field.

R. El Bitar; C. Salame; P. Mialhe

2007 Microelectronics International

doi: 10.1108/13565360710779217

Purpose – The purpose of this work is to highlight the evolutions of the switching times parameters of commercial vertical diffuse metal oxide semiconductor field effect transistors after a hot carrier injection in the reverse bias pn junction. Design/methodology/approach – Experiment was done basically by hot carrier injection, where a large drain‐source voltage V DS is applied to reverse bias the body drain junction, then inducing a 30 mA reverse current. The drain polarization was increased gradually, by steps of 0.5 V/s, up to desired V DS value in order to prevent sudden breakdown. Switching time parameters were measured at different temperatures and up to 300°C. Findings – The experimental results show that the device rise time decreases significantly for the first period of stress time at room temperature, which increases the speed of the device during this turn‐on switch. This event was associated with the high‐electric field in the junction region that pulls electrons from the oxide gate into the channel, thus leaving trapped holes in the oxide bulk due to their low mobility. Originality/value – This research study has an important value in terms of engineering application where speed of electronic devices is one of the most valuable parameters in the communication and information technology fields.

Farhad Sarvar; David C. Whalley; David A. Hutt; Paul J. Palmer; Nee Joo Teh

2007 Microelectronics International

doi: 10.1108/13565360710818439

Purpose – The encapsulation of electronic assemblies within thermoplastic polymers is an attractive technology for the protection of circuitry used in harsh environments, such as those experienced in automotive applications. However, the relatively low‐thermal conductivity of the encapsulating polymer will introduce a thermally insulating barrier, which will impact on the dissipation of heat from the components and may result in the build‐up of stresses in the structure. This paper therefore seeks to present the results from computational models used to investigate the thermal and thermo‐mechanical issues arising during the operation of such electronic modules. In particular, a two‐shot overmoulded structure comprising an inner layer of water soluble and an outer layer of conventional engineering thermoplastics was investigated, due to this type of structure's potential to enable the easy separation of the electronics from the polymer at the end‐of‐life for recycling. Design/methodology/approach – Representative finite element models of the overmoulded electronic structures were constructed and the effects of the polymer overmould were analysed through thermal and thermo‐mechanical simulations. Investigations were also carried out to explore the effect of materials properties on the overmoulded structure. Findings – Models have shown that some power de‐rating of components is required to prevent temperatures exceeding those in unencapsulated circuits and have quantified the benefits of adding thermally conductive fillers to the polymer. Simulations have also clearly demonstrated the benefits of foamed polymers in reducing thermal stresses in the assemblies, despite their poorer thermal conductivity compared with solid polymers. Originality/value – The paper illustrates the thermal issues affecting the overmoulded electronics and gives some guidelines for improving their performance.