Wang, Xinyu; Chen, Xinyu; Ma, Jingyi; Gou, Saifei; Guo, Xiaojiao; Tong, Ling; Zhu, Junqiang; Xia, Yin; Wang, Die; Sheng, Chuming; Chen, Honglei; Sun, Zhengzong; Ma, Shunli; Riaud, Antoine; Xu, Zihan; Cong, Chunxiao; Qiu, Zhijun; Zhou, Peng; Xie, Yufeng; Bian, Lifeng; Bao, Wenzhong
doi: 10.1002/adma.202270334pmid: N/A
Chen, Yulong; Tian, Ziao; Wang, Xiang; Ran, Nian; Wang, Chen; Cui, Anyang; Lu, Huihui; Zhang, Miao; Xue, Zhongying; Mei, Yongfeng; Chu, Paul K.; Liu, Jianjun; Hu, Zhigao; Di, Zengfeng
Liu, Chang‐Ju; Wan, Yi; Li, Lain‐Jong; Lin, Chih‐Pin; Hou, Tuo‐Hung; Huang, Zi‐Yuan; Hu, Vita Pi‐Ho
doi: 10.1002/adma.202107894pmid: 34932857
2D transition‐metal dichalcogenide semiconductors, such as MoS2 and WSe2, with adequate bandgaps are promising channel materials for ultrascaled logic transistors. This scalability study of 2D material (2DM)‐based field‐effect transistor (FET) and static random‐access memory (SRAM) cells analyzing the impact of layer thickness reveals that the monolayer 2DM FET with superior electrostatics is beneficial for its ability to mitigate the read–write conflict in an SRAM cell at scaled technology nodes (1–2.1 nm). Moreover, the monolayer 2DM SRAM exhibits lower cell read access time and write time than the bilayer and trilayer 2DM SRAM cells at fixed leakage power. This simulation predicts that the optimization of 2DM SRAM designed with state‐of‐the‐art contact resistance, mobility, and equivalent oxide thickness leads to excellent stability and operation speed at the 1‐nm node. Applying the nanosheet (NS) gate‐all‐around (GAA) structure to 2DM further reduces cell read access time and write time and improves the area density of the SRAM cells, demonstrating a feasible scaling path beyond Si technology using 2DM NSFETs. In addition to the device design, the process challenges for 2DM NSFETs, including the cost‐effective stacking of 2DM layers, formation of electrical contacts, suspended 2DM channels, and GAA structures, are also discussed.
Tian, Bo; Li, Junzhu; Samad, Abdus; Schwingenschlögl, Udo; Lanza, Mario; Zhang, Xixiang
doi: 10.1002/adma.202201253pmid: 35307871
In addition to conventional monolayer or bilayer graphene films, graphene‐mesh metamaterials have attracted considerable research attention within the scientific community owing to their unique physical and optical properties. Currently, most graphene‐mesh metamaterials are fabricated using common lithography techniques on exfoliated graphene flakes, which require the deposition and removal of chemicals during fabrication. This process may introduce contamination or doping, thereby limiting their production size and application in nanodevices. Herein, the controlled production of wafer‐scale high‐quality single‐crystal nucleus‐free graphene‐mesh metamaterial films with zigzag edges is demonstrated. The 13C‐isotopic labeling graphene‐growth approach, large‐area Raman mapping techniques, and a uniquely designed high‐voltage localized‐space air‐ionization etching method are utilized to directly remove the graphene nuclei. Subsequently, a hydrogen‐assisted anisotropic etching process is employed for transforming irregular edges into zigzag edges within the hexagonal‐shaped holes, producing a large‐scale single‐crystal high‐quality graphene‐mesh metamaterial film on a Cu(111) substrate. The carrier mobilities of the fabricated field‐effect transistors on the as‐produced films are measured. The findings of this study enable the large‐scale production of high‐quality low‐dimensional graphene‐mesh metamaterials and provide insights for the application of integrated circuits based on graphene and other 2D metamaterials.
Pasadas, Francisco; Feijoo, Pedro C.; Mavredakis, Nikolaos; Pacheco‐Sanchez, Aníbal; Chaves, Ferney A.; Jiménez, David
doi: 10.1002/adma.202201691pmid: 35593428
The progress made toward the definition of a modular compact modeling technology for graphene field‐effect transistors (GFETs) that enables the electrical analysis of arbitrary GFET‐based integrated circuits is reported. A set of primary models embracing the main physical principles defines the ideal GFET response under DC, transient (time domain), AC (frequency domain), and noise (frequency domain) analysis. Another set of secondary models accounts for the GFET non‐idealities, such as extrinsic‐, short‐channel‐, trapping/detrapping‐, self‐heating‐, and non‐quasi static‐effects, which can have a significant impact under static and/or dynamic operation. At both device and circuit levels, significant consistency is demonstrated between the simulation output and experimental data for relevant operating conditions. Additionally, a perspective of the challenges during the scale up of the GFET modeling technology toward higher technology readiness levels while drawing a collaborative scenario among fabrication technology groups, modeling groups, and circuit designers, is provided.
Saeed, Mohamed; Palacios, Paula; Wei, Muh‐Dey; Baskent, Eyyub; Fan, Chun‐Yu; Uzlu, Burkay; Wang, Kun‐Ta; Hemmetter, Andreas; Wang, Zhenxing; Neumaier, Daniel; Lemme, Max C.; Negra, Renato
doi: 10.1002/adma.202108473pmid: 34957614
Over the past two decades, research on 2D materials has received much interest. Graphene is the most promising candidate regarding high‐frequency applications thus far due to is high carrier mobility. Here, the research about the employment of graphene in micro‐ and millimeter‐wave circuits is reviewed. The review starts with the different methodologies to grow and transfer graphene, before discussing the way graphene‐based field‐effect‐transistors (GFETs) and diodes are built. A review on different approaches for realizing these devices is provided before discussing the employment of both GFETs and graphene diodes in different micro‐ and millimeter‐wave circuits, showing the possibilities but also the limitations of this 2D material for high‐frequency applications.
Wang, Shuiyuan; Liu, Xiaoxian; Zhou, Peng
doi: 10.1002/adma.202106886pmid: 34741478
Continued reduction in transistor size can improve the performance of silicon integrated circuits (ICs). However, as Moore's law approaches physical limits, high‐performance growth in silicon ICs becomes unsustainable, due to challenges of scaling, energy efficiency, and memory limitations. The ultrathin layers, diverse band structures, unique electronic properties, and silicon‐compatible processes of 2D materials create the potential to consistently drive advanced performance in ICs. Here, the potential of fusing 2D materials with silicon ICs to minimize the challenges in silicon ICs, and to create technologies beyond the von Neumann architecture, is presented, and the killer applications for 2D materials in logic and memory devices to ease scaling, energy efficiency bottlenecks, and memory dilemmas encountered in silicon ICs are discussed. The fusion of 2D materials allows the creation of all‐in‐one perception, memory, and computation technologies beyond the von Neumann architecture to enhance system efficiency and remove computing power bottlenecks. Progress on the 2D ICs demonstration is summarized, as well as the technical hurdles it faces in terms of wafer‐scale heterostructure growth, transfer, and compatible integration with silicon ICs. Finally, the promising pathways and obstacles to the technological advances in ICs due to the integration of 2D materials with silicon are presented.
Xiong, Xiong; Kang, Jiyang; Liu, Shiyuan; Tong, Anyu; Fu, Tianyue; Li, Xuefei; Huang, Ru; Wu, Yanqing
doi: 10.1002/adma.202270335pmid: N/A
Schram, Tom; Sutar, Surajit; Radu, Iuliana; Asselberghs, Inge
doi: 10.1002/adma.202109796pmid: 36071023
Large‐area 2D‐material‐based devices may find applications as sensor or photonics devices or can be incorporated in the back end of line (BEOL) to provide additional functionality. The introduction of highly scaled 2D‐based circuits for high‐performance logic applications in production is projected to be implemented after the Si‐sheet‐based CFET devices. Here, a view on the requirements needed for full wafer integration of aggressively scaled 2D‐based logic circuits, the status of developments, and the definition of the gaps to be bridged is provided. Today, typical test vehicles for 2D devices are single‐sheet devices fully integrated in a lab environment, but transfer to a more scaled device in a fab environment has been demonstrated. This work reviews the status of the module development, including considerations for setting up fab‐compatible process routes for single‐sheet devices. While further development on key modules is still required, substantial progress is made for MX2 channel growth, high‐k dielectric deposition, and contact engineering. Finally, the process requirements for building ultra‐scaled stacked nanosheets are also reflected on.
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