SIMULATION: Transactions of The Society for Modeling and Simulation International

Wildberger, A. Martin

doi: 10.1177/003754978704800601pmid: N/A

doi: 10.1177/003754978704800602pmid: N/A

Pratt, Charles A.

doi: 10.1177/003754978704800603pmid: N/A

Robinson, John P.; Wade, William D.; Leong, Peter K.; Mortara, Mary E.

doi: 10.1177/003754978704800604pmid: N/A

The design and test of error control encoding and decoding mod ules for simulating data communications systems is described. Generic application library modules for the Interactive Commu nications Systems Simulation Module (ICSSM) were developed for block and convolutional codes using the programming lan guage FORTRAN. The end user specifies a system for simulation study by linking various communications, signal processing and error control modules.In developing the encoding and decoding modules, a top-down approach resulted in a heirarchy of subroutines and function calls. This approach simplified the validation task and allowed easier upgrades and maintenance. Some of the design trade-offs for both the block code and convolutional code modules are viewed. It was found that modest use of storage can be traded for execution time. Various computations and operations can be efficiently accomplished with table look-up when using a high-level language such as FORTRAN.A simple communication system using these modules was studied. The error behavior was as expected. The key problems identified in this development were systems issues; primarily, module initialization and synchronization.

Park, Chan S.; Yong Deok Noh,

doi: 10.1177/003754978704800605pmid: N/A

A port simulation model (Monte Carlo type) is presented to simulate the future economic port capacity to meet projected cargo demand. The first part of the model determines the effects caused by the port capacity expansion. The second part evaluates the port economics due to changes in the port capacity. The simulation model was tested by applying it to the actual port expansion followed at the Port of Mobile in Alabama.

Ghosh, Sumit

doi: 10.1177/003754978704800606pmid: N/A

This paper presents the issue of dynamic multi-level simulation of hardware designs that addresses the problem of inefficiency associated with the conventional static multi-level simulation ap proaches as in ADLIB-SABLE (Hill 1980), DIANA (Demou and Arnout 1979), and SPLICE (Newton 1978). In this approach, digital sim ulation or verification (McWilliams 1980) of hardware designs is initiated at a high level of abstraction. When detailed results are required for one or more high-level components or for tracing the source of an error to any of the lower-level devices, the appropriate components are expanded into their lower-level implementations. Then simulation or verification initiates at that level. Following completion of execution at the lower level, con trol returns to the higher level. Consequently, only those sub parts of a digital design are selected for expansion and detailed simulation that are dynamically warranted by the higher-level simulation results. Unnecessary simulation effort may be elimi nated. Dynamic multi-level simulation or zooming is a generaliza tion of the swapping technique (Szygenda 1973) to functional and fault simulation and timing verification and to the differ ent abstraction levels in the hierarchy between the gate- and behavior-levels. This paper also addresses the implementation of zooming in the rule-based design verifier, RDV (Ghosh 1984), at Stanford University. That RDV uses Ada (U.S. Dept. of Defense 1983) as a hardware description language and simulation envi ronment (Ghosh 1985).

McLeod, John; McLeod, Suzette

doi: 10.1177/003754978704800607pmid: N/A