Leakage power loss is a major concern in deep-submicron technologies as it drains the battery even when a circuit is completely idle. In this paper, we first present a novel leakage reduction technique and then compare and contrast it with other well established leakage reduction techniques. Our leakage reduction technique achieves cancellation of leakage effects in both the pull-up network (PUN) as well as the pull-down network (PDN) for CMOS circuits. It involves voltage balancing in the PUN and PDN paths using a combination of high- V T (high voltage threshold) and standard- V T sleep transistors. Experiments conducted on a variety of multi-level combinational MCNC'91 benchmarks show significant savings in leakage power (upto 3 orders of magnitude), with lesser area and delay penalty using our leakage reduction technique when compared to other techniques.
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VCLEARIT: a VLSI CMOS circuit leakage reduction technique for nanoscale technologies
Lakshmikanthan, Preetham; Nuñez, Adrian
Follow ACM SIGARCH Computer Architecture News
, Volume 35 (5)
Association for Computing Machinery – Dec 1, 2007
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