Access the full text.
Sign up today, get DeepDyve free for 14 days.
References for this paper are not available at this time. We will be adding them shortly, thank you for your patience.
Usenet Nuggets Mark Thorson mmm@cup.portal.com This column consists of selected traffic from the c o m p . a r c h newsgroup, a forum for discussion of computer architecture on Usenet--the international network of Unixbased computers. As always, the opinions expressed in this column are the personal views of the authors, and do not necessarily represent the institutions to which they are affiliated. Text which sets the context of a message appears in italics; this is usually text the author has quoted from earlier Usenet traffic. The code-like expressions below the authors' names are their addresses on Usenet. recap the earlier discussions on the net: To a) If you have a barrel with N slots, then any single thread runs at approximately 1/N of the speed that it might if the thread owned the whole CPU. b) Each thread needs (for sure) its own set of: PC Integer & FP registers Privileged state registers c) Either each thread has its own MMU and cache---or it shares them with other threads. d) All of this likely shares a memory bus, which is likely to be a bottleneck anyway, unless you spend a lot of money. In any case,
ACM SIGARCH Computer Architecture News – Association for Computing Machinery
Published: Sep 1, 1992
Read and print from thousands of top scholarly journals.
Already have an account? Log in
Bookmark this article. You can see your Bookmarks on your DeepDyve Library.
To save an article, log in first, or sign up for a DeepDyve account if you don’t already have one.
Copy and paste the desired citation format or use the link below to download a file formatted for EndNote
Access the full text.
Sign up today, get DeepDyve free for 14 days.
All DeepDyve websites use cookies to improve your online experience. They were placed on your computer when you launched this website. You can change your cookie settings through your browser.