SIGDA newsletter, vol 17, number The application of simulated annealing techniques to logic synthesis was described by G. Whitcomb of UC Berkeley. This approach is interesting because of its clean separation of the optimization algorithm from the rules of Boolean algebra and calculation of circuit cost. Randomly selected transformation rules are applied to the circuit. Technology and timing considerations can be included in the cost function. The results are comparable to current algorithmic methods. However, there is room for improvement by including more complex transformation rules and detailed timing considerations in the cost function. The last formal session covered finite state machine synthesis. T. Sasao of Osaka University presented a method for partitioning combinational logic into many PLAs. Inputs to a PLA are broken into two sets and one PLA computes intermediate results from one set, forwarding these to the next PLA. A smaller total circuit area resulted for 19 of 25 examples. An interesting approach to state assignment was presented by R. Amann of the University of Karlsruhe. A loadable up-counter is used for the state bits. The objective is to find as many states as possible that can be assigned to consecutive states of the counter
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Trip report for the IEEE logic synthesis workshop
Micheli, Giovanni De
Follow ACM SIGDA Newsletter
, Volume 17 (3)
Association for Computing Machinery – Sep 1, 1987
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