Translation Hint Buffers To Reduce Access Time Of Physically-Addressed Instruction Caches Brian K. Bray and Michael J. Flynn Computer Systems Laboratory Stanford University ABSTRACT Virtual memory requires address translation to map a virtual address to a physical address. To reduce the performance penalty of address translation, the most recent address translations are cached in a translation lookaside buffer (TLB). To access a medium to large low-associative cache with the physical address, the TLB access must precede the cache access. To reduce the access time of a physicallyaddressed cache, a TLB subset called the TLBslice can be used. Only the bits that are used to address the cache need to be translated before the cache access, and the translation only needs to be a hint. The translated bits do not necessarily need to be correct since the cache miss handling hardware can stall the processor, and the cache access can be retried with the correct translation. However, with the TLBslice the reduced translation is still in series with the cache access. But, since the translation only needs to be a hint, translation can be predicted in parallel with address generation. This paper examines methods for predicting address translations for
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Translation hint buffers to reduce access time of physically-addressed instruction caches
Bray, Brian K.; Flynn, Michael J.
Follow ACM SIGMICRO Newsletter
, Volume 23 (1-2)
Association for Computing Machinery – Dec 10, 1992
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