Throughput in a Counterflow Pipeline Processor Aimee Severson and Brent Nelson Department of Electrical and Computer Engineering Brigham Young University Provo, UT 84604 aimee@ gccko.ee.byu.edu nelson@ee.byu.edu Abstract The Counterfiow Pipeline Processor, or CFPP, is a unique form of pipelined RISC architecture whose goal is to obtain regular and modular performance from a bi-directional pipeline. In this pipeline, instructions and results move in opposite directions in a counterflow fashion. A basic synchronous model of the CFPP was created and used to study configuration options which affect the flow of instructions and results through the pipeline. These options, which varied instruction execution, pipeline movement arbitration, and result movements, were varied in order to fred the configuration which maximized throughput for a set of benchmarks. 1 Introduction The Counterflow Pipeline Processor, or CFPP, is a processor proposed by Ivan Sutherland, Robert Sproull, and Charles Molnar as anew form of pipelined RISC architecture. Its goal is to obtain regular and modular performance with abidirectional pipeline, in which instructions flow in one direction and their results counterflow in the opposite direction. The inventors of this architectme emphasize several characteristics which could give it design or performance advantages over existing processors. Key characteristics include
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Throughput in a counterflow pipeline processor
Severson, Aimee; Nelson, Brent
Follow ACM SIGARCH Computer Architecture News
, Volume 23 (1)
Association for Computing Machinery – Mar 1, 1995
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