Memory access latency is the traditional bottleneck of system performance. Cache is historically introduced to bridge the big gap between processor and main memory so as to reduce the load-to-use delay. The traditional one cycle cache latency has already caused problems for pipeline execution. The situation becomes worse for modern deep pipelined superscalar processor when clock rate continues to increase and cache capacity increases, which inevitably lead to more cycle cache latency.Load address prediction could alleviate the load-to-use delay by predicting the target address of load instruction in the early stage of pipeline. But existing address prediction schemes can only predict up to 67% regular address pattern.To explore the potential of address prediction, in this paper, from the program behavior, we study and simulate various load address change patterns. Our results first show that the address of load has high repeatability. We further classify load instructions naturally into several categories and analyze their behavior respectively. The reason for both correct address prediction and incorrect prediction are studied from program behavior. The load instructions with low prediction rate are further analyzed. Focused on the high misprediction for load from stack scalar variable, one new prediction schemes: stack coloring is proposed. Furthermore, we also propose a new context predictor: global context predictor, which greatly saves the prediction resources. Our results show that the high predictability with 77.5%, 75.8% and 90.6% can be achieved for stride, context and hybrid predictor respectively.
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The predictability of load address
Zhang, Jinsuo
Follow ACM SIGARCH Computer Architecture News
, Volume 29 (4)
Association for Computing Machinery – Sep 1, 2001
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