The Memory Wall and the CMOS M a u r i c e V. W i l k e s Olivetti Research Cambridge, England mwilkes@cam-orl.co.uk End-Point In a recent note in Computer Architecture News (eel, 23 No, 1 March 1995) Wulf and McKee draw attention to the fact that the discrepancy between processor speed and DRAM access time is increasing. Since cache misses cannot be reduced to zero, if this trend continues the time will come when the rate of executing instructions will be determined by the rate at which instructions, not already in the cache, can be supplied by the DRAM. They express this by saying that we will hit a wall beyond which increases in processor speed do not increase the rate at which calculations can be performed. This raises the question of how long the substantial annual increases of speed to which we have become accustomed during the last 20 years can continue. Wulf and McKee remark that, over the past thirty years, there have been many p r e d i c t i o n s that the annual increases were about to come to an end, but all were based on false
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The memory wall and the CMOS end-point
Wilkes, Maurice V.
Follow ACM SIGARCH Computer Architecture News
, Volume 23 (4)
Association for Computing Machinery – Sep 1, 1995
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