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Journals ACM SIGARCH Computer Architecture News Volume 37 Issue 2

Many-core processor architectures require scalable solutions that reflect the locality and power constraints of future generations of silicon technology. This paper presents a many-core processor that supports an abstract model of concurrency, based on a Self-adaptive Virtual Processor (SVP). This processor implements instructions, which automatically map and schedule threads providing a code devoid of any explicit communication. The thrust of this approach is to produce binary code that is divorced from implementation parameters, yet, which still gives good performance over future generations of CMPs. A key component of this processor architecture is the memory system. This paper briefly presents the model and evaluates its memory architecture.

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The implementation of an SVP many-core processor and the evaluation of its memory architecture

Jesshope, Chris; Lankamp, Mike; Zhang, Li
ACM SIGARCH Computer Architecture News , Volume 37 (2)
Association for Computing Machinery – Jul 23, 2009

More Info
  • Publisher Association for Computing Machinery
  • Copyright The ACM Portal is published by the Association for Computing Machinery. Copyright © 2010 ACM, Inc.
  • Subject Design studies
  • ISSN 0163-5964
  • D.O.I. 10.1145/1577129.1577136
  • Publisher site Get PDF  

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