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The effect of employing advanced branching mechanisms in superscalar processors

The effect of employing advanced branching mechanisms in superscalar processors The Effect of Employing Advanced Branching Mechanisms in Superscalar Processors Yen-Jen Oyang, Chun-Hung Wen, Yu-Fen Chen, and Shu-May Lin Department of Computer Science and Information Engineering National Taiwan University Taipei, Taiwan Abstract This paper discusses the effect of employing advanced branching mechanisms in superscalar processors. The motivation behind employing advanced branching mechanisms in superscalar processors is to reduce the control dependence, or in other words the number of branch operations, in the program so that instruction-level parallelism can be exploited more effectively. The second effect achieved by reducing the control dependence in the program is a decrease of the amount of branch penalty due to less branch operations. In this paper, two advanced branching mechanisms are discussed. The first mechanism involves incorporating multiple condition registers in superscalar processors. The second mechanism is a novel multi-way branching scheme proposed in this paper. A quantitative analysis on the effect of the two branching mechanisms shows that incorporating multiple condition registers can boost the superscalar processor performance by a factor of 16% to 20% while employing the proposed multi-way branching mechanism can achieve even greater performance improvement, up to 47%. 1. Introduction Superscalar processors are processors that comprise multiple parallel execution http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png ACM SIGARCH Computer Architecture News Association for Computing Machinery

The effect of employing advanced branching mechanisms in superscalar processors

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References (11)

Publisher
Association for Computing Machinery
Copyright
Copyright © 1990 by ACM Inc.
ISSN
0163-5964
DOI
10.1145/121973.121978
Publisher site
See Article on Publisher Site

Abstract

The Effect of Employing Advanced Branching Mechanisms in Superscalar Processors Yen-Jen Oyang, Chun-Hung Wen, Yu-Fen Chen, and Shu-May Lin Department of Computer Science and Information Engineering National Taiwan University Taipei, Taiwan Abstract This paper discusses the effect of employing advanced branching mechanisms in superscalar processors. The motivation behind employing advanced branching mechanisms in superscalar processors is to reduce the control dependence, or in other words the number of branch operations, in the program so that instruction-level parallelism can be exploited more effectively. The second effect achieved by reducing the control dependence in the program is a decrease of the amount of branch penalty due to less branch operations. In this paper, two advanced branching mechanisms are discussed. The first mechanism involves incorporating multiple condition registers in superscalar processors. The second mechanism is a novel multi-way branching scheme proposed in this paper. A quantitative analysis on the effect of the two branching mechanisms shows that incorporating multiple condition registers can boost the superscalar processor performance by a factor of 16% to 20% while employing the proposed multi-way branching mechanism can achieve even greater performance improvement, up to 47%. 1. Introduction Superscalar processors are processors that comprise multiple parallel execution

Journal

ACM SIGARCH Computer Architecture News – Association for Computing Machinery

Published: Dec 2, 1990

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