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Journals ACM Computing Surveys (CSUR) Volume 38 Issue 3

Temporal logic model checking involves checking the state-space of a model of a system to determine whether errors can occur in the system. Often this involves checking symmetrically equivalent areas of the state-space. The use of symmetry reduction to increase the efficiency of model checking has inspired a wealth of activity in the area of model checking research. We provide a survey of the associated literature.

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Symmetry in temporal logic model checking

Miller, Alice; Donaldson, Alastair; Calder, Muffy
ACM Computing Surveys (CSUR) , Volume 38 (3)
Association for Computing Machinery – Sep 30, 2006

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