SpiNNaker: Design and Implementation of a GALS Multicore System-on-Chip LUIS A. PLANA, DAVID CLARK, SIMON DAVIDSON, STEVE FURBER, JIM GARSIDE, EUSTACE PAINKRAS, JEFFREY PEPPER, and STEVE TEMPLE, The University of Manchester JOHN BAINBRIDGE, Sil´stix ı The design and implementation of globally asynchronous locally synchronous systems-on-chip is a challenging activity. The large size and complexity of the systems require the use of computer-aided design (CAD) tools but, unfortunately, most tools do not work adequately with asynchronous circuits. This article describes the successful design and implementation of SpiNNaker, a GALS multicore system-on-chip. The process was completed using commercial CAD tools from synthesis to layout. A hierarchical methodology was devised to deal with the asynchronous sections of the system, encapsulating and validating timing assumptions at each level. The crossbar topology combined with a pipelined asynchronous fabric implementation allows the on-chip network to meet the stringent requirements of the system. The implementation methodology constrains the design in a way that allows the tools to complete their tasks successfully. A rst test chip, with reduced resources and complexity was taped-out using the proposed methodology. Test chips were received in December 2009 and were fully functional. The methodology had to be modi ed to
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SpiNNaker: Design and Implementation of a GALS Multicore System-on-Chip
Plana, Luis A.; Clark, David; Davidson, Simon; Furber, Steve; Garside, Jim; Painkras, Eustace; Pepper, Jeffrey; Temple, Steve; Bainbridge, John
Follow ACM Journal on Emerging Technologies in Computing Systems (JETC)
, Volume 7 (4)
Association for Computing Machinery – Dec 1, 2011
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