Software-Controlled On-Chip Memory for High-Performance and Low-Power Computing Masaaki KONDO Motonobu FUJITA Hiroshi NAKAMURA R e s e a r c h C e n t e r for A d v a n c e d S c i e n c e a n d T e c h n o l o g y , T h e U n i v e r s i t y of T o k y o E-marl: [kondo, mfujita, nakamura] @hal. rcast.u-tokyo, ac. jp 1 Motivation The performance gap between processor and main memory speed, called memory wall, is serious problem especially in High Performance Computing (HPC). This memory wall problem is addressed by two factors, large memory access latency and lack of memory throughput. There have been proposed many techniques for tolerating memory access latency, including cache prefetching. However, these techniques increase main memory traffic[l]. In order to overcome this problem, we have proposed a new processor architecture SCIMA (the abbreviation of Software Controlled Integrated Memory Architecture) which integrates software controllable memory (SCM) into a processor chip[2]. Our previous work revealed that SCIMA has the potential to tolerate memory latency without wasting memory bandwidth. Currently, we
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Software-controlled on-chip memory for high-performance and low-power computing
Kondo, Masaaki; Fujita, Motonobu; Nakamura, Hiroshi
Follow ACM SIGARCH Computer Architecture News
, Volume 30 (3)
Association for Computing Machinery – Jun 1, 2002
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