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Journals ACM SIGARCH Computer Architecture News Volume 27 Issue 3

Selective-Set-Invalidation(SSI) for Soft-Error-Resifient Cache Architecture Seung H. Hwang and Gwan S. Choi Department of Electrical Engineering Texas A&M University College Station, TX 77843, USA seunghwe @ee.tamu.edu / gchoi @ee.tamu.edu Abstract This paper proposes a novel cache-memory design for soft-error silence, and verifies the design through a simulation that uxes realistic system and software model 1 The S51 design is a combination o f an n-bit error detector and a fast circuit that allows real-time-forced invalidation of corrupted data sets. The current design supports the writethrough caching policy and will be extended f o r the writeback policy. To verify the effectiveness of the proposed design approach, mixed-mode simulations are conducted that insert soft-errors(bit-flips) into the cache-memory model. The simulation commences while running different class of programs (ALU-intensive and branch-intensive programs) designed to stress several key functions of the target systetrL System-level failure modes triggered by the soft errors are observed and all inserted errors are recovered by SSl scheme. The performance and layout-area overheads are also quantified. The worst-case performance/rime overhead of the $51 scheme is approximately 9% while the lay-outarea overhead is less than 0.5% 1. Introduction Cache m e m o r y is an essential

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Selective-set-invalidation (SSI) for soft-error-resilient cache architecture

Hwang, Seung H.; Choi, Gwan S.
ACM SIGARCH Computer Architecture News , Volume 27 (3)
Association for Computing Machinery – Jun 1, 1999

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