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Journals ACM SIGARCH Computer Architecture News Volume 25 Issue 5

RSIM: Rice Simulator for ILP Multiprocessors Vijay S. Pai, Paxthasarathy P~.nganathan, axtd Sarita V. Adve Department of Electrical and Computer Engineering Rice University Houston, Texas h t t p : / / w , m = e c e . rice. edu/,,~rs im We are pleased to announce the releaseof version 1.0 of RSIM: Rice Simulator for ILP Multiprocessors_ RSIM simulates shared-memory multiprocessors(and uniprocessors) bruit from processors that aggressively exploit instruction-level parallelism (ILP). RSIM is execution-driven and models staLe-of-the-art ILP processors, an aggressive memory system, and a mu]tiprocessor coherence protocol and interconnect, including contention at all resources. We have used KSIM in our research as well as in underl~raduate and graduate courses in computer architecture. Key Features of Simulated Systems RSIM provides many configuration parameters to allow the user to simulate a variety of shared-memory multiprocessor and uniprocessor architectures. Key features supported by RSIM are: ¢ Multiple outstanding cache requests ¢ Memory interleaving ¢ Softwaxe-controlled non-binding prefetching M u l t i p r o c e s s o r s y s t e m features: ¢ CC-NUMA sha~ed-memory system directory-barred cache-coherence protocol with ¢ Support for sequential consistency~ processor consistency, and release consistency ¢ Wormhole-routed mesh network Platforms RSIM i~as been run on SUN machines with Solari~ 2.5, SGI Power Challenges with IRIX 6.2, and a Convex Exemplar with HP-UX version 10. The applications to be simulated with RSIM must be compiled for SPAKC V9/Solaris 2.5 or 2.6, and must be linked with the included library. Obtaining RSIM RSIM version 1.0 is available at no cost for non-commercial use from the URL h t t p : / / r ~ w - e ce. rice. edu/~r s im/dist, ht~. P r o c e s s o r features; Multiple instructionissue Out-of-order (dynamic) scheduling Register renaming ¢ Staticand dynamic branch predictionsupport ¢ Non-blocking loads and stores More information about RSIM is also available from the above URL [1, 2]. ¢ Hardware memory disambiguation ¢ Str~ghtforward and optimized memory co.nsistency implementations M e m o r y hierarchy features~ ¢

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RSIM: Rice simulator for ILP multiprocessors

Pai, Vijay S.; Ranganathan, Parthasarathy; Adve, Sarita V.
ACM SIGARCH Computer Architecture News , Volume 25 (5)
Association for Computing Machinery – Dec 1, 1997

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