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Journals ACM SIGMICRO Newsletter Volume 23 Issue 1-2

Register Traffic Analysis for Streamlining Inter-Operation in Fine-Grain ParaIIei Processors Manoj Franklin and Gurindar S. Sohi Computer Sciences Department University of Wisconsin-Madison 1210 West Dayton Street Madison, WI 53706, USA Abstract Traditionally, register files have been the primary agent for inter-operation communication in load/store architectures. As processors start issuing multiple instructions per cycle, a centralized register file can easily become a bottleneck. This paper analyzes the register file traffic in a l&d/store architecture with a view to motivate the development of alternate inter-operation communication mechanisms that reduce the bandwidth demanded of a centralized register file. We first provide metrics to characterize the register traffic. These metrics deal with the degree and locality of use of the register instances created. We then present the results of a simulation study that uses the MIPS R2000 architecture and the SPEC benchmark programs. We have two major results. First, a large number of the register instances are used only once, and the average degree of use of register instances is about 2. Second, most of the register instances are used up soon after they are created (within about 30-40 instructions). This suggests that alternate inter-operation communication mechanisms that exploit the temporal locality

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Register traffic analysis for streamlining inter-operation communication in fine-grain parallel processors

Franklin, Manoj; Sohi, Gurindar S.
ACM SIGMICRO Newsletter , Volume 23 (1-2)
Association for Computing Machinery – Dec 10, 1992

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